An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang Macau University Good morning, My name is Guohe Yin, from Macau University. Today, my present topic is . 2017/4/23

Outline 1. Introduction to SAR ADC 2. Proposed ADC Architecture 3. Circuit Implementation 4. Simulation Results 5. Conclusions 2017/4/23 2

10 bit charge redistribution SAR ADC 1.The SAR ADC Advantages: Low power; Simple architecture; Middle area; Disadvantages: The capacitor ratio increase extremely with the resolution. So, for the 10-bit ADC, the MSB capacitor is 512C!! This is the 10-bit charge redistibution SAR ADC architecture, its principle is very simple. First, the cap sample the input signal, after this, the cap connect to refernce voltage, Vref and GND. And then, the MSB cap connect to Vref, the other cap connect to GND. Then the comparator compare the valus, if the result is 1, the switch keep in Vref, or to GND. And then, the conversion continue, until all bits are over. This adc have many advantage, …..also, disadvantage is ……. Here , this equation is the voltage. Based on this equation, we propose an new architecture ADC. We can devide this equation in two part. This part can be the first stage, and then this part consist of the second stage. Then the pipelined adc can work. 10 bit charge redistribution SAR ADC 2017/4/23

2. Proposed ADC Architecture This is the proposed 9-bit two-stage pipelined ADC architecture, it consist of 5-bit coarse and 5-bit fine stage. The clock generator generate the signal sample strobe to comparaor clear and sharing signal. The sample signal is to control the coarse stage sample the signal and Strobe is to reset and trigger the comparator in the coarse stage, the Strobe2 is to trigger the on in fine stage, before conversion ,the clear is to reset the cap in fine stage. Sharing signal is to control the coarse and fine stage to share the charge. Plus and minus Vrefp1 is the reference voltage, and Vrefp2 is the referece voltae in fine stage. After the conversion in every stage, just combine the last bit of coarse stage and the first bit in fine stage into one bit. Also double the reference voltage of the fine stage. Then we get the 9bit digital coeds. The proposed 9-bit two-stage pipelined ADC architecture 2017/4/23 4

2. Proposed ADC Architecture This is the timing diagram. First, the coare stage sample the signal, after the 5bit conversion in coarse stage begin,, then the two stage share the charge. Also before sharing phase, the fine stage should be cleared and reset. Then they work in pipelined fashion. Timing diagram of pipelined SAR ADC 2017/4/23 5

3. Switch scheme Advantages: MSB capacitor 16C, not 512C; No op-amp; Capacitive DAC arrays of the 10-bit pipelined SAR ADC 2017/4/23 6

3. Switch scheme Not Vcm!! Circuit diagram of MSB and LSB DAC arrays in sharing phase 2017/4/23 7

3. Switch scheme The output voltage of the DAC array: Before sharing phase, MSB-array voltage: After sharing phase, LSB-array voltage: 2017/4/23 8

3. Switch scheme MSB and LSB DAC arrays in sharing phase with determined LSB reference voltage 2017/4/23 9

4. Circuit Implementation 4.1 The comparator The Dynamic latch with Pre-amplifier gain 16. 2017/4/23 10

4. Circuit Implementation 4.2 Digital Error Correction To eliminate the offset of two comparators, the last bit of coarse and the first bit of the fine stage are combined into one bit for overlapping. 4.3 Successive Approximation Register (SAR) In this ADC, only 6-DFFs instead of 11 in SAR ADC, low digital power. 4.4 Reference Ladder Resistor/tap = 1.6 K Ohm Unit capacitance =16 fF for the DAC Array 2017/4/23 11

Fig.9 Simulated DNL and INL 5. Simulation Result The static performance DNL (differential nonlinearity) : +0.46/-0.66 LSB INL (integral nonlinearity) : +0.37/-0.53 LSB Fig.9 Simulated DNL and INL 2017/4/23 12

5. Simulation Result Fig.10. FFT of the digital output @ fin=403.3 kHz and fS =1 MS/s. Fig.11. Histogram of SNDR of proposed novel ADC @ fin =484.4 KHz and fS =1 MS/s. Fig.12. Simulated SNDR versus input frequency @ fS =1 MS/s. Fig.13. Simulated SNDR versus sampling rate. 2017/4/23 13

Performance table Technology 65 nm Power Supply 1 V Resolution 9 bit Power Dissipation Sampling Rate 1 MS/s Analog 4.371 μW Dynamic Range 1.0 Vp-p. diff Digital 0.791 μW SNDR(@fin=484.4kHz) 53.0 dB Reference ladder 5.098 μW DNL (LSB) +0.46/-0.66 Total Power 10.26 μW INL (LSB) +0.37/-0.53 FOM 28.3 fJ/conv-s 2017/4/23 14

References 1. X. Zou, X. Xu, L. Yao, Y. Lian, “ A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip,” IEEE J. Solid State Circuits, vol. 44, no.4, pp. 1067 - 1077, Apr. 2009. 2. C. Liu, S. Chang, G. Huang, Yi. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid State Circuits, vol. 45, no.4, pp. 731 – 740, Apr. 2010. 3. A. M. Abo, P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipelined analog-to-digital converter,” IEEE J. Solid State Circuits, vol. 34, no. 5, pp. 599-606, May 1999. 4. M. V. Elzakker, V. E. Tuijl , P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, “A 10-bit Charge-Redistribution ADC Consuming 1.9 uW at 1 MS/s,” IEEE J. Solid State Circuits, vol. 45, no.5, pp. 1007 – 1015, May 2010. 5. G. Y. Huang, C. C. Liu; Y. Z. Lin, S. J. Chang, "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," Procs. IEEE ASSCC, pp. 157 - 160, Dec. 2009. 6. J. Craninckx, G. van der Plas, “A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 246–247, Feb. 2007. 2017/4/23

Conclusions A 9-bit 1 MS/s SAR ADC with pipelined architecture is presented: 1) Reduce the digital power 2) The total capacitance is 2*32C instead of 512C; 3) No operational amplifier The ADC consumes power 10.26 μW, and achieves the FOM 28.3 fJ/conversion-step. 2017/4/23 16

Thank you! 2017/4/23