SIGMA-DELTA ADC SD16_A Sigma-Delta ADC Shruthi Sujendra

Digital Filters in Sigma-Delta ADC

Digital Filters in Sigma-Delta ADC… For example :  Input  sine wave  Output  measure the amplitude and phase Sinc filter is a simple digital filter which can average each block of OSR bits and is called so because of its frequency response. Sinc (x) = sin(x)/x

Digital Filters in Sigma-Delta ADC…

The Final Result from a Sigma–Delta ADC

Features of Sigma–Delta Converters Input characteristics Anti aliasing performance Differential inputs Programmable gain amplifier Latency Frequency response

Features of Sigma–Delta Converters…  Input characteristics There must be enough time for the capacitance to charge. The input is switched at a high frequency (fm).  Anti aliasing performance Does not provide good anti aliasing A filter whose amplitude is reasonably flat at low frequency before falling rapidly to a low value for f>=1/2fs is required.

Features of Sigma–Delta Converters…  Differential Inputs Sigma-delta ADCs have differential inputs.  Programmable Gain Amplifier Eliminates the need for an external op-amp. They amplify voltage by using charges and capacitors. A separate buffer may be provided to boost the input impedance.

Features of Sigma–Delta Converters…  Latency

Features of Sigma–Delta Converters…  Frequency response It follows from the slow response in time that the frequency response is also poor. This is important given that sigma-delta converters are used for high precision.

SD16_A Sigma-Delta ADC  The MSP430 currently offers 3 varieties of 16 bit sigma-delta ADC 1.The original module SD16, which contains 3 independent channels. 2.SD16_A, which has only a single core but a multiplexer on the input. 3.The latest module is a combination of these two.

Architecture of SD16_A

1.Input channels 2.Input pins 3.High impedance buffer 4.Programmable gain amplifier 5.Reference voltage 6.Sigma-delta converter 7.Clock 8.Interrupts 9.Conversion trigger 10.Supply voltage

Input channels 8 possible channels selected according to SD16INCHx bits. Inputs are differential pairs. 3 internal channels – 1.Potential divider which monitors the supply voltage V5 = (VCC−VSS)/11 2.Channel 6 is connected to a temperature sensor. 3.Channel 7 inputs are short-circuited. This allows us to measure the offset voltage of the system and this is subtracted from measured values.

Input Pins The enabling of connection between the SD16_A and the pins are done in many ways. Anti aliasing filter should be provided on analog inputs. Cut off frequency of 10KHz or less for fm=1MHz and OSR=256. Lower frequency can be used to reduce noise when input varies slowly.

High Impedance Buffer Used if the signal is not taken from a source with low impedance. A voltage follower circuit with an op-amp except that it has both differential inputs and outputs. SD16BUFx bits are used to select different currents which needs to match the speed of the modulator.

Programmable Gain Amplifier Offers a gain of 1-32 in powers of 2. SD16GAINx bits. Important for input characteristics. Uses switched capacitors rather than op-am and resistors. The gains are not accurate except for unity.

Reference Voltage SD16REFON is used to enable an internal 1.2V reference. SD16VMIDON is used to turn on the output buffer, which is used for reference voltage outside MSP430. SD16REFON and SD16VMIDON bits need to be cleared to use an external voltage between 1.0 and 1.5V.

Sigma-Delta Converter Second-order modulator with a sinc3 digital filter. The OSR is set by SD16OSRx bits in SD16; this is used to give OSR = 32,64, 128 and 256. SD16_A has a SD16XOSR bit used to increase ratio to 512 or The converter has a low power mode selected using SD16LP bit.

Clock The clock is taken from MCLK, SMCLK, ACLK. Timer_A uses TACLK. SD16 has no internal oscillator. If SD16LP is set the minimum frequency is 30KHz and maximum frequency is reduced to 0.5MHz. Frequency of clock input 1.SD16DIVx  2,4,8 2.SD16XDIVx  3,16,48

Interrupts There is a single interrupt vector with two sources in the SD16_A1.  SD16IFG is set when a new converted result is available in SD16MEM0. There is a flag for each converter channel in larger SD16s.  SD16OVIFG is set when an overrun occurs, which means that a new value has been written to a conversion memory before the previous value was read. It does not show which channel overflowed in SD16s with multiple converters.

Conversion Trigger 1.Single conversion  SD16SC The SD16 performs the number of conversions specified by the SD16INTDLYx bits, raises the interrupt flag SD16IFG, clears SD16SC, and stops. single conversion is slightly misleading because the final result in SD16MEM0 is not usually the result of only a single conversion, but depends on SD16INTDLYx.

Conversion Trigger … 2.Continuous conversion  SD16SC Continues till SD16SC is cleared. The SD16 does not complete the current conversion, which means that a false value may be left in SD16MEM0.

Supply Voltage SD16_A needs VCC ≥ 2.5V in the F20x3, a more restricted range than many other peripherals. The specification for the SD16 is even more stringent at VCC ≥ 2.7V.

Features of the SD16_A include 16-bit sigma-delta architecture Up to eight multiplexed differential analog inputs per channel (The number of inputs is device dependent, see the device- specific datasheet.) Software selectable on-chip reference voltage generation (1.2V) Software selectable internal or external reference Built-in temperature sensor Up to 1.1 MHz modulator input frequency High impedance input buffer (not implemented on all devices, see the device-specific data sheet) Selectable low-power conversion mode