Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Integration of ancillaries with DAQ Goal Context Specifications, modes Design Schedule & cost Ch. Theisen for the ADWG

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Goal Integration of ancillary detectors electronics with Agata Provide an interface  As many ancillary detectors as possible !

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Context When: for the demonstrator phase (2007) Where: Ganil, GSI, JYFL, Köln, LNL Who: Existing and/or identified ancillaries  ADWG meeting 22/06/2004  LUSIA, FRS, RFD, Neutron Wall, CUP, VAMOS, PRISMA, GREAT,…, γ arrays  List to finalize a.s.a.p…

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb LUSIA FRS RFD Neutron Wall

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb CUP VAMOS PRISMA RITU/GREAT

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Specifications  Correlate ancillaries with Agata (event number and/or clock counter)  Event filtering Keep relevant Agata and ancillary det. events “Slow-down” Agata Reduce ancillary det. dead-time  Interaction with AGATA GTS

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb How –LUSIAVME –FRSVME –RFDVME –Neutron WallVME –CUPVME –VAMOSVME –PRISMAVME –GREATVME –γ arraysVME  VME INTERFACE

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Interface with GTS GTSAncillary Trigger Request Val/Rej, Clock Val/Rej : combination of ancillary/Agata : “master”, “slave”, “mixed” modes Latency times  NOT A TRIGGER MODULE !

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Latency times Val/Rej : latency > 7μs Too late for most converters  Dead time !  Need prompt pre-trigger  Request to ADP : Agata prompt signal

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Global scheme Ancillary Front-end Ancillary Readout VME interface Trigger Request Val/Rej Clock counter Event Number GTS supervisor Agata Merge/ Ancillary post-merge Agata flow Agata prompt signal

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Three modes “Slow” conversion mode (common dead time) “Fast” conversion mode (parallel-like) Trigger-less (TDR)

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Slow conversion mode Trigger_Request Local_Trigger Local_Trigger_Tag Busy ADC conversion Validation_Rejection_Tag Interface VME Cycle Event_Number TR LT TAG Busy Val/Rej Val/Rej TAG Trigger_Validation or Trigger_Reject Only if trigger validated

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Busy2 “Fast” conversion mode”: parallel like Trigger_Request Local_Trigger Local_Trigger_Tag Busy ADC conversion Validation_Rejection_Tag Interface VME Cycle Event_Number TR1 LT1 TAG1 Busy1 Val/Rej1 Val/Rej TAG1 TAG2 LT2 TR2 Val/Rej2 Val/Rej TAG2 Trigger_Validation or Trigger_Reject

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb TDR (JYFL) mode Correlated data (DSSD, Gas) : Trigger request Uncorrelated data (Tunnel, Focal plane Ge…) No events: only data  Time Stamping Clock counter correlation ! TDR clock counter GTS clock counter  Embedded TDR data source

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb TDR mode Interface provides 100MHz clock Embedded TDR data source –Phase calibration –Time-stamp synchronisation –Time-stamp alignment  Interface with TDR metronome  Shark link

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Design: layout Mezzanine FPGA Optical fiber Ethernet I/O Jtag Bus Backplane memory Ethernet Shark

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb VIRTEX - II PRO XC2V7 FF672 (396 I/O) VIRTEX - II PRO XC2V7 FF672 (396 I/O) BANK_4 BANK_1 BANK_0 BANK_6 BANK_7 BANK_5 BANK_3 BANK_2. CR_CON1 CR_CON2 GTS_JTAG LSA_Trace_GTS CPU_TraceGTS LSA_Trace_VME CPU_TraceVME P1_VMEP2_VME Data Bus – [32] Address Bus - [31] Address Modifier – [6] Adr_, Data_Str – [3] LWORD, WRITE – [2] DTACK, BERR – [2] IRQ – [4] IACK,IN,OUT –[3] SYSRESET – [1] VXI -- [36] ? [3] TOTAL: [120] Front Panel Drive/Conv FRONT Trigger Request Local Trigger Veto Reject Validate Backpreasure LEDs CCLK [2] Inspection [4] ESTIMATE [20] SDRAM Ethernet POWER Shark-link [7] Metronome [4] Trigger_Req [1] Local_Trigger – [1] Trigger_Val/_Rej – [2] Local_Trig_Tag – [8] Clock_deskew – [6] GTS_Clock – [2] Val/Rej_Tag – [8] LLP_Status – [8] GTS_Status – [8] MSG_Out(Str) – [8(+1)] FPGA_Progr – [6] TOTAL: [75] LSA_Trace - [36] CPU_Trace – [16] Clock_IN – [2] Bcast_in(Str) – [8(+1)] TOTAL: [73]

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Schedule Main task: Krakow + Ganil (tests, real time soft.), Padova (GTS), Daresbury (TDR)

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Cost 2 prototypes : 6 k€ Production : 2.5 k€ /cards *6 = 15 k€ Prototypes + Production = 21 k€ + GTS Mezzanines 2.3 k€/board Total = 34.8 k€ with 6 mezzanines = 29.4 k€ with 4 mezzanines

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Common dead-time vs. Agata Losses ! Ancillary: Common dead-time Agata: Full parallel Future (post-demonstrator): switch to parallel read-out

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Conclusions Preliminary specifications ready We need feedback; contact us ! Mailing list: please register ! Web site (  GSI official site)

Ancillary Detectors Working Group Agata Week/GSI, 23 Feb Contributors D. Bazzacco, P. Bednarczyk, M. Bellato, P.J. Coleman-Smith, A. Czermak, B. Dulny, A. Gadea, R. Isocrate, P. Jones, L. Olivier, V. Pucknell, Ch. Theisen, G. Wittwer, M. Zieblinski