Booster Cogging Upgrades Craig Drennan, Kiyomi Seiya, Alex Waller

RF cogging to momentum cogging current cogging-RF cogging momentum cogging hardware requirements Replace cogging board with new board switch to MFC board status

Why do we need cogging? Gap for the extraction kicker Booster is going to extract 12 pulses every 15Hz for the Nova operation. Booster notch position supposes to synchronize to the MI injection. MI 1 revolution 1 st pulse 2 nd pulse Time

Move notch creation earlier Intensity B field 1 st pulse2 nd pulse 400  7msec The notch was created at 7msec for the 2-12 th pulse. Creating the notch at lower energy can reduce beam loss in the Booster.

Bucket difference between Booster and MI MI inj. freq. : Hz The bending field in the Booster, injection energy, timing, rf feedback …..are changing from pulse to pulse and bucket position at extraction is not constant.

Current cogging – RF cogging – (1) 7msec Final bucket position -Predicts final bucket position by measuring Gradient1, 2. -Sends RPOS offset which is required for the frequency changes. The revolution frequency difference between reference cycle and cycle with B field error. 1 2

Current cogging – RF cogging – (2) Transition energy RPOS offset Final bucket position +/- 10 buckets

Fixed with RPOS feedback Changed by dipole corrector Dipole corrector: 24.4[A] B field error ~1% can be compensated. Momentum cogging B+dB Keeps the orbit centered and saves aperture. Has two feedback loops for frequency and RPOS. (Assuming 10[A] change )

 f rev with RF cogging and Momentum cogging

Counts: ΔC[turn] diff_rev_ freq ΔCn-1[turn], ΔCn[turn] Calculates gain for RPOs offsets. Calculates gain for corrector current. DSPFPGAB dot MI rev marker Booster rev m DAC Radial offset DAC Dipole correctors RPOS feed back Cogging board Momentum cogging (before 7msec) RF cogging (after 7msec) Notch pulse

Control for the dipole corrector offseet Current curve 1 short-H-1 H-short01 Σ DAC Need cable, amplifier and timing for all 48 corrector. C473 PS Cogging MFC DAC Amp/msec

Switching to new board Current Cogging boardMFC board DSP SHARC FPGA ALTERA

AD/LLRF group has been developing this board for the last 10 years. It is similar to the current cogging board. (VXI based ALTERA FPGA) Current cogging board has one spare. Some parts are no longer available. Spec: 32 * 12-bit, 65MS/S ADC input channels including 2 DC coupled channels 1 * 14-bit105MS/S ADC input channel 4 * 14-bit 260 MS/S DAC channels configurable as AC or DC coupled 1 * 8 output clock divider chip with a 1.6 GHz max external clock input 1 * External Aux clock input (LVCMOS) to FPGA and/or DAC 2 * Front panel TTL trigger inputs Multi‐cavity Field Control (MFC) Module

Booster LLRF VXI crate : slot 0 2: beam power 3: Digital freq. reference 4: Para Phase 5: Cogging 6: pulse to Cogging

Resource Manager Booster LLRF VXI crate frequency curve -Logical address (SC) Beam power (SC) Para phase (SC) RF Cogging (SC) new cogging with MFC board (DC) FPGA and DSP codes setup environments on PC. header, library, compiler….. Slot 0 card new Motorola compiler Communication between slot 0 card and DSP old: slot 0  shared memory  DSP new: slot 0   DSP Status of the new board

RF cogging on the new board. (before shutdown) Setup offset control for dipole corrector. (during shutdown) Add momentum cogging. (during shutdown) Beam studies and simulations. (on going) Future Plan