Comments on Lab #4 Annotating Timing Diagrams Draw viewer’s attention to the points you are trying to show / verify –Important output states glitch or no glitch here Particular result you expected or wanted to verify –Events that caused important outcomes Which input conditions (important “test vectors”)?

Comments on Lab #4 Annotating Timing Diagrams Draw viewer’s attention to the points you are trying to show / verify USING: –Causal arrows annotation –Circle or highlight –Add notes with arrows pointing to where you see it in diagram –(Your own ideas to CLEARLY & OBVIOUSLY point things out.)

Experiment 5 Procedure Overview Analyze “unknown” circuit using a Logic Analyzer Design and Implement an equivalent function on Nexys board using VHDL

Logic Analyzer Tool to debug an actual digital circuit Actual circuits seldom initially work as expected LA output is primarily a timing diagram that displays the states of designated signals in a circuit. Examples: Last week’s experiment and this one: –Exp 4: Timing Diagram from Simulation (B2 Spice) –Exp 5: Timing Diagram from Physical Circuit (LA) Timing Diagram from Simulation (ModelSim) SORRY! “That’s life” in the “real” world!!

Logic Analyzer Operation LA takes “snapshots” (samples) of circuit conditions at certain intervals. Interpolates sample points to produce timing diagram Complete example provided in Experiment 5 introduction

The Trigger The trigger is a description of the circuit conditions you intend on viewing. Logic Analyzer fills and updates half of storage memory while waiting for the trigger event –Filled with data that occurs before the trigger. The other half of the storage memory is filled with sample points that occur after the trigger conditions are met

Example of LA Operation data t0 data t1 data t2 data t15 data t16 data t17 data t18 data t19 data t7 data t6 data t2 data t1 data t0 data t3 data t4 data t5 data t10 data t9 data t8 Trigger Found!

Connecting Logic Analyzer Wire Connections YOU must make

Nexys Board JA JB JC

Nexys-2 Board

Xilinx Design Methodology The steps required in order to model, simulate and implement a circuit using the Xilinx ISE software Basic steps are as simple or as complicated as you want to make them Xilinx ISE and VHDL used again in CPE 229/269/329 and CSC 315

Basic Xilinx Design Flow 1) VHDL source code generates a description of circuit. 2) VHDL source is translated into intermediate form for use by other software used in the design flow. 3) Test Bench Waveform software generates signals to verify circuit operation using the ModelSim XE simulator. 4) Circuit inputs and outputs are “mapped” to FPGA pins externally hardwired to I/O devices on the Nexys board. 5) The circuit design is downloaded into the FPGA. (Use Digilent ExPORT for Nexys USB port) 6) Proper operation of the circuit is verified.

Create a New VHDL Source Module & Define Inputs/Outputs

Insert code here Add your logic expression to the VHDL code module template Your definition of input / output signals is turned into a VHDL “Entity”

Insert code here

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Use the marker to check the truth table

Experiment 5 - Procedure Steps 1.Connect the Nexys board to the LA interface (wires) 2.Setup the Logic Analyzer (display, trigger, etc.) 3.Download the test file to Nexys 4.Use the logic analyzer to obtain the Timing Waveform. 5.From that waveform, generate the Truth Table (2 functions) 6.Perform a K-Map reduction 7.Write out the logic equation for your truth table for VHDL coding (Compact minterm, reduced SOP) 8.Create a VHDL project, using the process in the Exp 5 Procedures. 9.Add your 2 functions to the VHDL source code file. 10.Use the Xilinx tools to compile the code & synthesize a circuit. 11.Verify the circuit using the ModelSim simulator 12.Download the.bit file and manually verify your solution.

A Little “Sage Advice” Since this is your first time using the tools, be sure to follow all of the steps, in the order given.Since this is your first time using the tools, be sure to follow all of the steps, in the order given. –Skipping steps may result in horrendously hideous outcomes that you really don’t want to experience. –A confused CAD tool is not a happy CAD tool! ;( Be sure to read the Explanations as you proceed, so that you begin to understand why you are doing what you are doing Be sure to read the Explanations as you proceed, so that you begin to understand why you are doing what you are doing.

FOR NEXT WEEK Be sure to read ahead and understand the entire Lab Procedure & Background –Especially the operation of the 2 devices you need to design Bring a draft of the VHDL code for your BCD-to-7segment Decoder with you to Lab –Design AHEAD OF TIME …or you probably won’t finish!! –Use text editor, Xilinx ISE tools or hand write

So, for today… “Go for it!...” See what happens … Ask questions when things don’t make sense! WORK QUICKLY!! … and have fun!

Circuit connections to development board