Low Power via Sub-Threshold Circuits Mike Pridgen.

Slides:

Advertisements

Similar presentations

Copyright © 2004 by Miguel A. Marin Revised CMOS CIRCUIT TECHNOLOGY NMOS & PMOS TRANSISTOR SWITCH NMOS & PMOS AS LOGIC CIRCUITS NMOS & PMOS.

Advertisements

Transmission Gate Based Circuits

Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)

Robust Low Power VLSI R obust L ow P ower VLSI Sub-threshold Sense Amplifier (SA) Compensation Using Auto-zeroing Circuitry 01/21/2014 Peter Beshay Department.

Power Reduction Techniques For Microprocessor Systems

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University.

MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.

Digital Integrated Circuits© Prentice Hall 1995 Devices The MOS Transistor.

A Leakage Current Replica Keeper for Dynamic Circuits  Based on the work presented in “A leakage Current Replica Keeper for Dynamic Circuits” by: Yolin.

Leakage-Biased Domino Circuits for Dynamic Fine- Grain Leakage Reduction Seongmoo Heo and Krste Asanović Massachusetts Institute of Technology Lab for.

SEQUENTIAL LOGIC Digital Integrated Circuits© Prentice Hall 1995 Introduction.

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

A Self-adjusting Scheme to Determine Optimum RBB by Monitoring Leakage Currents Nikhil Jayakumar* Sandeep Dhar $ Sunil P. Khatri* $ National Semiconductor,

© Digital Integrated Circuits 2nd Inverter CMOS Inverter: Digital Workhorse  Best Figures of Merit in CMOS Family  Noise Immunity  Performance  Power/Buffer.

Physical States for Bits. Black Box Representations.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

1 adaptive body bias for reducing process variations nuno alves 19 / october / 2006.

Lecture 5 – Power Prof. Luke Theogarajan

Introduction to CMOS VLSI Design Nonideal Transistors.

Lecture 7: Power.

Lecture 7: Power.

1 Computing with Leakage Currents Nikhil Jayakumar, Kanupriya Gulati, Rajesh Garg and Sunil P. Khatri ECE Department Texas A&M University.

© Digital Integrated Circuits 2nd Devices VLSI Devices  Intuitive understanding of device operation  Fundamental analytic models  Manual Models  Spice.

Power, Energy and Delay Static CMOS is an attractive design style because of its good noise margins, ideal voltage transfer characteristics, full logic.

The CMOS Inverter Slides adapted from:

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Advanced Computing and Information Systems laboratory Device Variability Impact on Logic Gate Failure Rates Erin Taylor and José Fortes Department of Electrical.

EE466: VLSI Design Power Dissipation. Outline Motivation to estimate power dissipation Sources of power dissipation Dynamic power dissipation Static power.

Mary Jane Irwin ( ) CSE477 VLSI Digital Circuits Fall 2002 Lecture 04: CMOS Inverter (static view) Mary Jane.

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

By: Jabulani Nyathi Washington State University School of EECS April 30, 2009 Circuits and Architectures to Deliver Low Power and High Speed Systems.

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style Sumeer Goel, Ashok Kumar, and Magdy A. Bayoumi.

ENGG 6090 Topic Review1 How to reduce the power dissipation? Switching Activity Switched Capacitance Voltage Scaling.

EE415 VLSI Design DYNAMIC LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

A Class Presentation for VLSI Course by : Fatemeh Refan Based on the work Leakage Power Analysis and Comparison of Deep Submicron Logic Gates Geoff Merrett.

THE INVERTERS. DIGITAL GATES Fundamental Parameters l Functionality l Reliability, Robustness l Area l Performance »Speed (delay) »Power Consumption »Energy.

1 Power Dissipation in CMOS Two Components contribute to the power dissipation: »Static Power Dissipation –Leakage current –Sub-threshold current »Dynamic.

Sub-threshold Design of Ultra Low Power CMOS Circuits Students: Dmitry Vaysman Alexander Gertsman Supervisors: Prof. Natan Kopeika Prof. Orly Yadid-Pecht.

CMOS DYNAMIC LOGIC DESIGN

16-1 McGraw-Hill Copyright © 2001 by the McGraw-Hill Companies, Inc. All rights reserved. Chapter Sixteen MOSFET Digital Circuits.

Power Management for Nanopower Sensor Applications Michael Seeman EE 241 Final Project Spring 2005 UC Berkeley.

A 256kb Sub-threshold SRAM in 65nm CMOS

ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static CMOS Logic ECE442: Digital Electronics.

CSE477 L07 Pass Transistor Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 07: Pass Transistor Logic Mary Jane Irwin (

Leakage reduction techniques Three major leakage current components 1. Gate leakage ; ~ Vdd 4 2. Subthreshold ; ~ Vdd 3 3. P/N junction.

EE141 © Digital Integrated Circuits 2nd Devices 1 Lecture 5. CMOS Device (cont.) ECE 407/507.

EE141 © Digital Integrated Circuits 2nd Devices 1 Goal of this lecture  Present understanding of device operation  nMOS/pMOS as switches  How to design.

Inverter Chapter 5 The Inverter April 10, Inverter Objective of This Chapter  Use Inverter to know basic CMOS Circuits Operations  Watch for performance.

EE141 © Digital Integrated Circuits 2nd Inverter 1 Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje.

Digital Integrated Circuits A Design Perspective

Basics of Energy & Power Dissipation

An Introduction to VLSI (Very Large Scale Integrated) Circuit Design

Low-Power BIST (Built-In Self Test) Overview 10/31/2014

Patricia Gonzalez Divya Akella VLSI Class Project.

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS inverters

Solid-State Devices & Circuits

Static CMOS Logic Seating chart updates

1 Very Low Voltage Operation of Benchmark Circuit c6288 Presented By: - Murali Dharan.

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 6.1 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng.

FEMTO-JOULE SWITCHING Review of Low Energy Approaches for the Nano Era Jabulani Nyathi Washington State University Valeriu Beiu Washington State University.

Seok-jae, Lee VLSI Signal Processing Lab. Korea University

1 Dynamic CMOS Chapter 9 of Textbook. 2 Dynamic CMOS  In static circuits at every point in time (except when switching) the output is connected to either.

EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Dynamic CMOS LogicDynamic CMOS Logic V1.0 5/4/2003.

CSE477 L06 Static CMOS Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 06: Static CMOS Logic Mary Jane Irwin (

Presentation transcript:

Low Power via Sub-Threshold Circuits Mike Pridgen

“Logic Circuits Operating in Subthreshold Voltages” – Jabulani Nyathi and Brent Bero “Sub-Threshold Design: The Challenges of Minimizing Circuit Energy” – B.H. Calhoun, A. Wang, N. Verma, and A. Chandrakasan 2

Goal of Sub-Threshold Circuits Minimize energy – Utilize leakage currents – Sacrifice speed 3

Uses of Sub-Threshold Circuits Standalone, low power devices – Wireless sensor nodes – RFID tags Burst-mode applications – Short, intensive bursts – Long, near-idle periods 4

Sub-Threshold FFT 16 bit FFT FFT lengths of 128 to mV V DD 10kHz 155nJ / FFT – 350x better than microprocessor – 8x better than ASIC 5

Improving Performance by Changing V BULK nMos – V BULK = 600mV pMos – V BULK = 0V 0 – 380mV I D increases by 10x Never “OFF” – I D > 0.1nA 6

Body Biasing Types Traditional Three main variations – SBB – DTMOS – ABB Plus many others 7

Traditional Biasing nMos V BULK = GND pMOS V BULK = V DD Traditional CMOS Inverter 8

Switched Body Biasing nMos V BULK = V DD pMos V BULK = GND V DD < V TH SBB CMOS Inverter 9

Dynamic Threshold V BULK = V G Off if V DD > V TH DTMOS Inverter 10

Adjustable Bulk Bias V DD < V TH V DD > V TH Tunable – Low Power – High Speed – TBB TBB Inverter 11

Shorter Delays 12 6 – 10x speedup

Improving Performance Increased V DD = Increased Speed V DD =.75V TH versus V DD =.5V TH – 8x faster Bias scheme irrelevant – More power 13

Noise Effects TBB versus Traditional V DD = 376.2mV Logic 0 – 0 to 200mV Logic 1 – 225 to 376.2mV SBB noise margins worse 14

Standard (6T) SRAM Adjacent cells leakage current Fails Static Noise Margins 15

Conclusions Bias schemes increase performance Speed versus Power Slight increase in noise 6T SRAMS unusable 16

Questions