SMU Report: R&D work for LAr upgrade May 4, UCSC Optical link for LAr upgrade readout Objectives: 1.Evaluate the 0.25  m Silicon on Sapphire (SOS) technology (Peregrine Semiconductor) for the LOC ASIC (done in ) 2.Design the link-on-chip (LOC) ASIC version 1 (LOC1), a “prove of principle” chip. (done in ) 3.Test LOC1. (in progress for 2007) 4.Design and test LOC2, a user chip. ( ) 5.Irradiation evaluation on link components: VCSELs, fibers (in progress in 2007) Manpower: One FTE, two RAs in a team of three FTEs, two RAs and two faculty members.

SMU Report: R&D work for LAr upgrade May 4, UCSC Evaluation of the 0.25  m SOS technology (1) 1.Three gamma (Co-60) tests for total dose effect (TID) and one proton test (for SEE and TID) were carried out on a dedicated test chip. 2.The gamma TID tests were carried out at BNL (many thanks to Jim Kierstead and Francesco) on the transistor array which contains 48 NMOS, 48 PMOS, with 4 types of different layouts, to study the leakage current and threshold voltage change in ionizing irradiation. 3.The proton (230 MeV) SEE test was carried out at MGH on the shift registers. 4.Results submitted to NSREC, RADECS and NASA symposiums. Image of the dedicated test chip. The transistor array is used for TID test. The shift register is used for SEE test. PLL components, ring oscillator are used to measure parameters for LOC1 design. Peregrine offered 50% discount of $40k, as a $20k in-kind support to this project. We share all results up to 100 krad with them.

SMU Report: R&D work for LAr upgrade May 4, UCSC Evaluation of the 0.25  m SOS technology (2) 5.Results from gamma (Co-60) TID tests. oTwo types of tests were carried out: With the sapphire substrate floating to study leakage current sources. With the substrate grounded during irradiation, a way we’ve found to control the leakage current and threshold voltage change in radiation. oLeakage current sources: oBack channel leakage has always been a concern in SOS and SOI technology. With the grounded substrate, the leakage current increase and threshold voltage change in our test chip during irradiation up to 4 Mrad are very small and not a concern.  This 0.25  m SOS technology is very rad-hard. NMOSPMOS NMOSPMOS Back channel leakage contribution is 70% in NMOS, 15% in PMOS. Side leakage can be mitigated with layout techniques (like the ELT), Back channel has been controlled through expensive fabrication process. With a grounded substrate, the leakage current increase is controlled below 250 nA. Threshold voltage increase is small and simulated to be within fabrication variations. A mechanism is proposed, under study with GEANT. A provisional patent has been filed from SMU.

SMU Report: R&D work for LAr upgrade May 4, UCSC Evaluation of the 0.25  m SOS technology (3) 6.Proton test oSource: 230 MeV proton, 1.9×10 13 proton/cm 2 oTests: TID up to 106 Mrad (Si); SEE cross section (probability). oResults: TID:  survives the TID test of 106 Mrad(Si) SEE:  very small SEE cross section. Test Element TypeFluence(proton/cm­ 2 ) Error Count #Cross section(cm 2 ) Std Shift Register18× <5.6× ELT Shift Register18× <5.6× Res. Hard Shift Register18× <5.6× SET free logic latch18× <5.6× Vcontrol(V)

SMU Report: R&D work for LAr upgrade May 4, UCSC Tests on fiber and VCSEL The Fiber: oInfinicor SX+ 50/250  m/1.6mm MM 10G fiber from Corning. Germanium doped. oTested wit Gamma (Co-60) and Proton (230 MeV, 1.9×10 13 proton/cm 2 ). oVery small light loss at low flux (dose rate). Big loss at high flux but anneals very quickly (within 1 hour) back. oVery promising for LHC upgrade. oMore tests with gamma needed. The VCSEL: oTwo HFE (10G LC w/ 50 ohm flex) from Finisar tested. oIrradiated with 230 MeV proton, 1.9×10 13 proton/cm 2. oThe VCSELs are biased during irradiations. oEye diagram – see plots and table. oLooks very promising but more tests needed. VCSEL Before irradiationAfter irradiation Rise/fall time (ps) O-power (  W) Rise/fall time (ps) O-power (  W) L1114/ / L2120/ / L1, before irradiation L1, after irradiation

SMU Report: R&D work for LAr upgrade May 4, UCSC LOC1 design and submission 1.Status: oPrototype chip with the clock unit (PLL), serializer, laser driver, designed and submitted in Feb Chip will be back to SMU May 16, oOne self-biasing PLL (1.25GHz), one LC PLL (4GHz) are also placed on this chip for irradiation tests, for component level studies for future higher speed designs. 2.Goal: oEvaluate the LOC design, perform in-lab tests, and rad-hard tests at system level. oProvide a test chip to work on fiber attachment at chip level. 3.Spec: o2.5 Gbps – Gbps. 4.Submission cost: $34k. Peregrine offered 15% discount from $40k, as an in-kind $6k contribution to this program that they are also interested in.

SMU Report: R&D work for LAr upgrade May 4, UCSC Conclusions on the SOS evaluation and the LOC1 design SOS technology evaluation: 1.Peregrine 0.25  m silicon-on-sapphire technology is rad-hard for LAr readout upgrade ASIC development. 2.SEE cross section based on shift registers is found to be less than 5.6× for 230 MeV protons. LOC1 ASIC design and submission: 1.A prototype serializer ASIC, the LOC1, has been designed and submitted. The design speed of this ASIC is 2.5 – Gbps. 2.LOC1 is not a user chip, it is only meant for the “proof of principle” for key components and their integration in the LOC design concept. 3.LC-based PLL with a central frequency of 4 GHz has been implemented in the same submission for future higher speed designs. Other components in the link: We have preliminary candidates for the VCSEL and the fiber.

SMU Report: R&D work for LAr upgrade May 4, UCSC Plans for 2007 and In-lab and irradiation tests on LOC1 (2007) oPreparation for LOC1 tests: design PCBs to carry LOC1. incorporate the board in our existing test systems already developed to test the GOL. Change VHDL code to record more information in irradiation tests. oPlan: In-lab function tests on LOC1: May – August Irradiation tests (gamma, proton) on LOC1, including data analysis: Sept. – December Preliminary reliability studies may also be carried out. Sept – March Fiber attachment studies (2007 – 2008): oThree attachment schemes will be studied, including flip-chip bonding. oFor serial data speeds around 3 Gbps, industrial standard packaged VCSEL module is preferred for fiber coupling. oAttracted local small companies to submit SBIR proposals on fiber coupling studies. 3.Design and evaluation of LOC2 (2008 – 2009): oDesign of LOC2 will start after we finish testing LOC1. oLOC2 will be a user chip. Close interaction with the “users” will be needed to define the interface and functionalities. At that time, we will need to address issues like the reference clock frequency, jitter and data bus width, signal standards (CMOS or LVDS), etc. We expect a much longer design period for LOC2 than for LOC1 because of these issues. oChip packaging issue will be addressed with LOC2. oLOC2 will be fully evaluated in a link system, in radiation environment. Reliability tests will be carried out with packaged chips.

SMU Report: R&D work for LAr upgrade May 4, UCSC Budget (for 2008) Manpower (1)One $55k/yr, w/ 25% benefit$68.75k Manpower (2) Two RA EE students, $1,500/mon/student. For two: $36k/yr, w/ 32% tuition benefit. $47.5k M&S (1)LOC2 submission$40k M&S (2) PCB fab, flip-chip/wire bonding, components for LOC2 test $15k TravelFor irradiation tests only$5k OthersReliability test$0 TotalWith SMU 45.5% overhead$256.4k Scenario one, LOC2 design and submission in FY 2008:

SMU Report: R&D work for LAr upgrade May 4, UCSC Budget (for 2008) Manpower (1)One $55k/yr, w/ 25% benefit$68.75k Manpower (2) Two RA EE students, $1,500/mon/student. For two: $36k/yr, w/ 32% tuition benefit. $47.5k TotalWith SMU 45.5% overhead$169.1k Scenario two, LOC2 design in 2008 but submit for fabrication in FY 2009: