1 Power Dissipation in CMOS Two Components contribute to the power dissipation: »Static Power Dissipation –Leakage current –Sub-threshold current »Dynamic Power Dissipation –Short circuit power dissipation –Charging and discharging power dissipation

2 Static Power Dissipation G S D D G S Vo VDD GND B B MP MN Leakage Current: P-N junction reverse biased current: i o = i s (e qV/kT -1) Typical value 0.1nA to temp. Total Power dissipation: P sl =  i 0.V DD Sub-threshold Current Relatively high in low threshold devices Vin

3 Analysis of CMOS circuit power dissipation n The power dissipation in a CMOS logic gate can be n expressed as n P = P static + P dynamic n = (VDD · I leakage ) + (p · f · E dynamic ) n Where p is the switching probability or activity factor n at the output node (i.e. the average number of output n switching events per clock cycle). n The dynamic energy consumed per output switching event is defined as E dynamic =

4 Analysis of CMOS circuit power dissipation The first term —— the energy dissipation due to the Charging/discharging of the effective load capacitance C L. The second term —— the energy dissipation due to the input-to- output coupling capacitance. A rising input results in a V DD  - V DD transition of the voltage across C M and so doubles the charge of C M. C L = C load + C dbp +C dbn C M = C gdn + C gdp

5 n distributed, n voltage-dependent, and n nonlinear. n So their exact modeling is quite complex. The MOSFET parasitic capacitances Even E SC can be modeled, it is also difficult to calculate the E dynamic. On the other hand, if the short-circuit current i SC can be Modeled, the power-supply current i DD may be modeled with the same method. So there is a possibility to directly model i DD instead of i SC.

6 Schematic of the Inverter

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8 The short-circuit energy dissipation E SC is due to the rail- to-rail current when both the PMOS and NMOS devices are simultaneously on. E SC = E SC_C + E SC_n Where and Analysis of short-circuit current

9 Charging and discharging currents n Discharging Inverter Charging Inverter

10 Factors that affect the short-circuit current For a long-channel device, assuming that the inverter is symmetrical (  n =  p =  and V Tn = -V Tp = V T ) and with zero load capacitance, and input signal has equal rise and fall times (  r =  f =  ), the average short-circuit current [Veendrick, 1994] is From the above equation, some fundamental factors that affect short-circuit current are: , V DD, V T,  and T.

11 Parameters affecting short cct current For a short-channel device,  and VT are no longer constants, but affected by a large number of parameters (i.e. circuit conditions, hspice parameters and process parameters). C L also affects short-circuit current. I mean is a function of the following parameters (t ox is process- dependent): C L, , T (or  /T), V DD, W n,p, L n,p (or W n,p / L n,p ), t ox, … The above argument is validated by the means of simulation in the case of discharging inverter,

12 The effect of C L on Short CCt Current

13 Effect of t r on short cct Current

14 Effect of Wp on Short cct Current

15 Effect of timestep setting on simulation results

16 Thank you !