MAPS readout Systems Christoph Schrader Dresden

Micro- Vertex Detector MAPS (“Monolithic Area Pixel Sensors”) Fig.1: Sketch of the proposed CBM experiment Micro- Vertex Detector: consists of two MAPS detector stations ~ 20µs integration time ~ 20µm pixel pitch  20 Gb/cm 2 raw data

Vertex Demonstrator in 12 seconds  1 Gb Fig.2: Example for MAPS-chip with 4 matrices Our MAPS-Chip (Mimosa-17): consists of four matrices with parallel readout 256 x 256 pixel/matrix pixel by pixel readout 1 ms readout speed/frame

TRBv2 and the add-on concept TRBv2: Etrax-FS-Processor Ethernet-connectivity an optical link with 2 Gbit/s programmable logic (Vertex 4) Fig.3: The general-propose trigger and readout board (TRBv2) Fig.4: The MDC-add-on mounted on the TRBv2 – back side

Duties and responsibilities of the TRBv2 for the MAPS add-on High data-rate digital interface connector (15Gbit/s) FPGA configuration High data transfer with optical link (2Gbit/s) Application process interface (API) Power supply +5V,10A Clock distribution

System configuration of MAPS readout serves as support for the various versions of MAPS devices adapts/converts the signals control and collect measurement data Fig.5: A block diagram of system configuration for MAPS readout

Add-on board design AUXILIARY BOARD ADD-ON BOARD TRBv2 Fig.6: Diagram of the add-on components

Correlated double sampling Data compression Threshold Data processing

Pipelining as data processing Fig.7: Data processing way

readout cycle ADC units ∆ ADC acquisition cycle Fig.8: The behaviour of SB-pixels is observed by frames. The constant current leakage in the capacitor is compensate through a diode. After hit the diode re-fill the capacitor Fig.10: After CDS clear hit identification is possible f x :p x f x-1 :p x (f x :p x - f x-1 :p x ) (f x-1 :p x - f x-2 :p x ) hit Correlated double sampling by Self-Bias-Pixel Fig.9: Equivalent circuit diagram of SB-Pixel 1900 threshold

Correlated double sampling and data compression Correlated double sampling: for noise reduction difference between the actual frame and the frame before Fig.11: Different between the pixel by FIFO and SDRAM Data compression

Threshold The hit and the 8 neighbour pixel are important Result: not the complete matrix is readout, only the hit with the neighbour pixel Fig.12: Data selection with threshold

Project status Board design (schematics) Layout is advanced Test the board hardware Data processing concept Data processing code (simulation)

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Add-on board design Fig.11: Add-on board

Simulation of Self-Bias-Pixel readout

readouto cycle ADC units ∆ ADC cycle Fig.9: The behaviour of 3T-pixels is observed by frames. The constant wastage is produced from the current leakage in the capacitor. Fig.10: Past baseline the leakage current is cut out f x :p x f x-1 :p x (f x :p x - f x-1 :p x ) (f x-1 :p x - f x-2 :p x ) hit Correlated double sampling by 3T-Pixel Fig.8: Equivalent circuit diagram