An ASIC Design methodology with Predictably Low Leakage, using Leakage-immune Standard Cells Nikhil Jayakumar, Sunil P Khatri ISLPED’03

outline Introduction Introduction Research about leakage power reduction Research about leakage power reduction State assignment and leakage power State assignment and leakage power Approach and design methodology Approach and design methodology Result Result Conclusion Conclusion

Introduction Importance of leakage currents control Importance of leakage currents control Leakage current I ds : Leakage current I ds : Voltage scaling and Voltage scaling and threshold voltage scaling )1( )()( 0 t ds t off V T V gs V v V nv ds eeI L W I    D S G B

Leakage reduction Source biasing Source biasing Using body effect case V t ↑ but performance ↓ Using body effect case V t ↑ but performance ↓ Stack effect Stack effect Direct V t manipulation Direct V t manipulation Dual V t partition Dual V t partition MTCMOS MTCMOS VTCMOS VTCMOS

Leakage reduction Source biasing Source biasing Using body effect case V t ↓buperformance↑ Using body effect case V t ↓buperformance↑ Stack effect Stack effect Direct V t manipulation Direct V t manipulation Dual V t partition Dual V t partition MTCMOS MTCMOS VTCMOS VTCMOS

State & voltage assignment (DAC 03) State dependence of a leakage current State dependence of a leakage current Find the best input vector for standby state Find the best input vector for standby state accuratly estimate Leakage of designs accuratly estimate Leakage of designs

State & voltage assignment (DAC 03) State dependence of a leakage current State dependence of a leakage current

State & voltage assignment (DAC 03) Without any state assignment Without any state assignment 0.31ns0.36ns 9.6nA 4.7nA

State & voltage assignment (DAC 03) Optimal input state with Vt assignment Optimal input state with Vt assignment 0.31ns 9.6nA0.99nA

MTCMOS & state assignment MTCMOS better than traditional standard cells design MTCMOS better than traditional standard cells design Not support predictable leakage currents Not support predictable leakage currents Two variants of standard cell Two variants of standard cell H variant for output “high” H variant for output “high” L variant for output “low” L variant for output “low”

MTCMOS & state assignment L variant of 3-NANDH variant of 3-NAND

Layout floorplan of HL gates Regular standard- cell L variant of a standard-cell H variant of a standard-cell

Design flow Traditional mapping using regular standard cells Determine a set of primary input assignment Simulate to find output of each gate Replace each gate by its output value Standard cell library Modified Standard cell library Place and route

Experimental results HL cell versus MT cell

Experimental results HL/MT cells versus regular cells

Leakage/area/delay comparison Precisely estimate leakage Precisely estimate leakage

Leakage/area/delay comparison Using exact timing analysis by run “sense” in SIS Using exact timing analysis by run “sense” in SIS HL 10% MT 12.5% delay overhead HL 10% MT 12.5% delay overhead

Leakage/area/delay comparison Using SE to P&R Using SE to P&R HL 11-21% overhead but 17% less than MTCMOS HL 11-21% overhead but 17% less than MTCMOS

Conclusions Low and predictable leakage value Low and predictable leakage value Better algo. To determine the best primary input vector Better algo. To determine the best primary input vector Improve overhead Improve overhead