A. Matsuzawa, Tokyo Tech. 1 Nano-scale CMOS and Low Voltage Analog to Digital Converter Design Challenges Akira Matsuzawa Tokyo Institute of Technology

A. Matsuzawa, Tokyo Tech. 2 Contents 1. Introduction 2.Effect of technology scaling on analog performance --- Performance analysis of pipeline ADC Design challenges for ADC in nano-scale era --- No use of Operational amplifier -- - Comparator controlled current source - Successive approximation ADC - Sub-ranging ADC 4. Summary

A. Matsuzawa, Tokyo Tech. 3 Performance and applications Resolution (bits) Conversion Rate (MHz) HDD/DVD Graphics Audio General Purpose DVC/DSC/Printer Video/ Communication Servo (µ-Computer) Automobile Meter Pipeline ADC Pipeline ADC is the major conversion architecture for communications and digital consumer products.

A. Matsuzawa, Tokyo Tech. 4 Pipeline ADC 1 st stage 2 nd Stage Sample Amp. Sample Amp. Sample Amp. Sample Amp. Transfer characteristics HoldSampleAmplify -V ref +V ref -V ref +V ref 01 Ｘ２ -V ref +V ref -V ref +V ref 0101 Ｘ２ 1 st Stage2 nd Stage Folding I/O characteristics makes higher resolution along with pipeline stages.

A. Matsuzawa, Tokyo Tech. 5 Speed and power b 12b Conversion speed has saturated at 200 MHz Smaller mW/MHz is needed for low power operation. 0.3mW/MHz for 10bit and 1mW/MHz for 12bit are the bottom lines. 200MHz

A. Matsuzawa, Tokyo Tech. 6 Effect of technology scaling on analog performance Technology scaling and performance of pipeline ADC

A. Matsuzawa, Tokyo Tech. 7 Operating voltage trend Operating voltage (V) Design rule (nm) Design Rule Analog High Analog Low Digital Low (Low leak) Digital High ITRS 2003 ITRS 2001 About 1V operation Operating voltage of scaled device will keep about 1V

A. Matsuzawa, Tokyo Tech. 8 Operational amplifier for ADC V in+ v out- v out+ 2V eff Vs=V dd -4V eff 2V eff V in- V dd Output signal range Gain Boost amp. Pipeline ADC needs high performance amplifier. The output signal range will be reduced along with voltage lowering. V s =V dd -0.7V V s dd =1.2V V s dd =1.0V

A. Matsuzawa, Tokyo Tech. 9 Requirements for operational amplifier Sampling Amplify N:ADC resolution M ： Stage resolution for 1.5b pipeline ADC DC gain Closed loop gain-bandwidth Higher resolution requires higher open loop gain. Higher conversion frequency requires higher closed loop GBW.

A. Matsuzawa, Tokyo Tech. 10 kT/C noise R CLCL Larger SNR requires larger capacitance and larger signal swing. Low signal swing increases required capacitance. CLCL v out φ vnvn 14bit 12bit 10bit V FS =5V V FS =3V V FS =2V V FS =1V n=2 SNR (dB) Capacitance (pF) n: configuration coefficient

A. Matsuzawa, Tokyo Tech. 11 Effect of technology scaling GBW: 10GHz GBW: 2GHz Conversion freq. : 1GHz Conversion freq. : 200MHz 90nm 0.25um Gain bandwidth of OpAmp increases along with technology scaling. However, can we increase every needed performances for ADCs?

A. Matsuzawa, Tokyo Tech. 12 Technology scaling for analog Signal Cap. Parasitic Cap. Parasitic Cap. Parasitic Cap. Parasitic Cap. Parasitic Cap. Parasitic Cap. Signal Cap. Technology scaling Technology scaling can reduce parasitic capacitances. However signal capacitance will increase to keep the same SNR at lower voltage operation. Parasitic capacitance  smaller Operating voltage  lower Signal swing  lower Signal capacitance  larger Voltage gain  lower

A. Matsuzawa, Tokyo Tech. 13 Performance model for pipeline ADC OpAmp A. Matsuzawa, “Analog IC Technologies for Future Wireless Systems,” IEICE, Tan on Electronics, Vol. E89- C, No.4, pp , April, We have developed the performance model for pipeline ADC that can treat technology scaling.

A. Matsuzawa, Tokyo Tech. 14 Scaling and analog device and circuit parameters (b)C pi_N, C pi_P, C po [fF/mA],ω p2_N,ω p2_P [GHz] (a)W N,W P [μm/mA],V A_N, V A_P [V] V eff =0.175V DR L[μm] C gd C gs Cap. [fF/mA],f T [GHz] W[μm/mA] fTfT W S: Scaling factor Gate width and capacitances decrease with technology scaling.

A. Matsuzawa, Tokyo Tech. 15 Determination of signal capacitance 90nm0.13μm0.18μm0.25μm0.35μm V dd 1.2V1.5V1.8V2.5V3.3V V sig_pp 1.0V1.6V2.2V3.6V5.2V DR[μm] C o [pF] 8bit 10bit 12bit 14bit V in+ v out- v out + 2V eff V dd -4V eff 2V eff V in- V dd Output signal range Gain Boost amp. Larger resolution requires larger signal capacitance. Furthermore, Voltage lowering increases signal capacitance more.

A. Matsuzawa, Tokyo Tech. 16 Performance curve ① C o ≫ C po,C pi ② C pi <C o ＜ C po ③ C o ＜ C po 、 C o ＜ C pi ① ③ ② Performance exhibits convex curve. There is the peak conversion frequency and the optimum current. Current increase results in increase of parasitic capacitances and decrease of conversion frequency in the higher current region.

A. Matsuzawa, Tokyo Tech bit 0.13μm90nm 0.13um attains highest conversion frequency in a low current region. However 90nm is over striding 0.13um along with increase of the current.

A. Matsuzawa, Tokyo Tech μm 10 bit 0.35μm0.18μm0.13μm90nm The best design rule depends on operating current. 0.35um attains highest conversion frequency in low operating current region!

A. Matsuzawa, Tokyo Tech bit 0.35μm0.25μm0.18μm Relaxed design rule is suitable for wider current range.

A. Matsuzawa, Tokyo Tech bit Scaled CMOS is not suitable for higher resolution ADC.

A. Matsuzawa, Tokyo Tech. 21 Performance summary 12bit ８ bit 10bit 12bit14bit Scaled CMOS is effective for just low resolution ADC. Scaled CMOS is not effective for high resolution ADC.

A. Matsuzawa, Tokyo Tech. 22 Voltage gain LV operation LV operation V A decreases with scaling and operating voltage lowering. High gain can not be expected. NMOS PMOS

A. Matsuzawa, Tokyo Tech. 23 Voltage gain of operational amplifier V in+ v out- v out+ V in- Gain Boost amp. 20dB 40dB Total gain is Voltage gain of OpAmp for scaled CMOS and LV operation is 80dB at most. Less than 10 bit ADC can be designed with scaled and low voltage CMOS.

A. Matsuzawa, Tokyo Tech. 24 Design challenges for ADC in nano-scale era --- No use of Operational amplifier -- - Comparator controlled current source - Successive approximation ADC - Sub-ranging ADC

A. Matsuzawa, Tokyo Tech. 25 I sink RR RR Design rule and Speed in Comparator Gain bandwidth (=Speed) is inversely proportional to the L 2 (channel length). Technology scaling is still effective to increase the comparator speed and to reduce operating current. Furthermore, low voltage operation, such as 0.5V, is available.

A. Matsuzawa, Tokyo Tech. 26 Comparator controlled current source V x is reaching the virtual ground voltage asymptotically Conventional OpAmp V x is reaching the virtual ground voltage with constant rate Comparator controlled current source T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator- Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp Feb Comparator controlled current source can realize the virtual ground. Now challenge for not use of OpAmp in ADC design has started.

A. Matsuzawa, Tokyo Tech. 27 Realistic comparator controlled current source I 2 << I 1 T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp Feb Time delay (V x  V o ) causes voltage offset. Small inverse current source has been introduced. The offset voltage can be reduced and does not effect the conversion linearity. 10b, 8MHz ADC has been developed. Pd=2.5mW. Lowest Pd/MHz

A. Matsuzawa, Tokyo Tech. 28 Successive approximation ADC D. Draxelmayr, “A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS,” IEEE, ISSCC 2004, Dig. of Tech. Papers, pp , Feb Eight interleaved SA-ADCs with 90nm CMOS attain 600MHz operation. Successive approximation ADC SA-ADC Successive approximation ADC has been used long time as a low power and low speed ADC. It doesn’t require OpAmp but capacitor array and comparator. Thus this architecture looks suitable for scaled and low voltage CMOS. Now challenge for renewal of this conventional architecture has started.

A. Matsuzawa, Tokyo Tech. 29 Improvement of SA-ADC S. W. M. Chen and R. W. Brodersen, “A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13um CMOS,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp Feb bit 600MHz 5.3mW ADC has been realized with 0.13um CMOS Asynchronous clock increases conversion frequency. Use of proper radix reduces capacitance. Capacitor ladder with some radix number Asynchronous clock

A. Matsuzawa, Tokyo Tech. 30 Sub-ranging ADC 7]Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A. Ogawa, “ A 30mw 12b 40MS/s Subranging ADC with a High-Gain Offset-Canceling Positive-Feedback Amplifier in 90nm Digital CMOS,” IEEE, ISSCC 2006, Dig. of Tech. Papers, pp Feb Sub-ranging ADC also doesn't require OpAmp and suitable for LV operation. However it requires low offset voltage comparators. Use of positive feedback technique has realized low offset voltage. Positive Feedback CKT Pd/MHz =0.75mW/MHz which is lowest value!! Technology revival has been found.

A. Matsuzawa, Tokyo Tech. 31 Summary Technology scaling is effective for increasing analog performance if not so much higher SNR is required. Technology scaling is not effective for increasing analog performance if higher SNR is required, and sometimes degrades it. Increase of signal capacitance to keep the SNR high at low voltage operation is essential serious issue for use of scaled CMOS. Furthermore, Gain lowering of OpAmp due to technology scaling and voltage lowering becomes serious issues. Design challenges for ADC has been started. No use of OpAmp is a common idea. Technology revivals have been found and the performance has been improved. Further improvement will be expected in future.