ECE2030 Introduction to Computer Engineering Lecture 12: Building Blocks for Combinational Logic (3) Adders/Subtractors, Parity Checkers Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

Half Adder (1-bit) ABS(um)C(arry) Half Adder AB S C

Half Adder (1-bit) ABS(um)C(arry) A B Sum Carry

Full Adder CinABS(um)Cout Full Adder AB S Cout Carry In (Cin)

Full Adder CinABS(um)Cout Cin AB Cin AB Cin AB Or

Full Adder A B Cin Cout S H.A.

Full Adder Cout S Half Adder S C A B Half Adder S C A B B A Cin

4-bit Ripple Adder using Full Adder Full Adder AB Cin Cout S S0 A0B0 Full Adder AB Cin Cout S S1 A1B1 Full Adder AB Cin Cout S S2 A2B2 Full Adder AB Cin Cout S S3 A3B3 Carry A B S C Half Adder A B Cin Cout S H.A. Full Adder

Full Adder Propagation Delay S0 A0B0 Carry Cin 1 st Stage Critical Path = 3 gate delays = D XOR +D AND +D OR

Full Adder Propagation Delay S0 A0B0 Cin S1 A1B1 2 nd Stage Critical Path = 2 gate delays = D AND +D OR (Since 1 st Critical path > D XOR ) 1 st Stage Critical Path = 3 gate delays = D XOR +D AND +D OR

Issue of 4-bit Ripple Adder Critical Path = D XOR +4*(D AND +D OR ) for 4-bit ripple adder (9 gate levels) For an N-bit ripple adder Critical Path Delay  ~ 2(N-1)+3 = (2N+1) Gate delays S0 A0B0 Cin S1 A1B1 S2 A2B2 S3 A3B3 Carry

Issue of Ripple Adder Carry propagationCarry propagation is the main issue in an N- bit ripple adder A faster adder needs to address the serial propagation of the carry bit Let’s re-examine the equation for full adders

GeneratePropagate Carry Generate & Propagate Note that all the carry’s are only dependent on input A and B and C

4-bit Carry-Lookahead Adder (CLA) Carry Lookahead Logic g1p1 A1B1 S1C1g2p2 A2B2 S2C2g3p3 A3B3 S3C3 g0p0 A0B0 S0C0C4

Inefficient Inefficient Implementation of Carry Lookahead Logic A0B0S0A1B1S1 C0 A2B2S2A3B3 S3 Reuse some gate output results  Little Improvement Carry Delay is 4*D AND + 2*D OR for Carry C 4

Implementation of Carry Lookahead Logic C4 A0B0S0A1B1S1 C0 A2B2S2A3B3 S3 Carry Lookahead Logic Only 3 Gate Delay for each Carry C i = D AND + 2*D OR 4 Gate Delay for each Sum S i = D AND + 2*D OR + D XOR

Cascading CLA Similar to ripple adder, but different latency CLA AB Cin Cout S S[3:0] A[3:0]B[3:0] CLA AB Cin Cout S S[7:4] A[7:4]B[7:4] CLA AB Cin Cout S S[11:8] A[11:8]B[11:8] 4 44 CLA AB Cin Cout S S[15:12] A[15:12]B[15:12] 4 44 Delay of each stage is 3 gate levels instead of 9 of ripple adders

Subtractor Design A – B = A + (-B) –Take 2’s complement of B –Perform addition of A and 2’s complement of B Full Adder AB Cin Cout S S0 A0 Full Adder AB Cin Cout S S1 A1 Full Adder AB Cin Cout S S2 A2 Full Adder AB Cin Cout S S3 A3 B0B1B2B3 C Subtract

Overflow/Underflow for Signed Arithmetic (+72) (+57) (+129) What is largest positive number represented by 8-bit? 8-bit Signed number addition (-127) ( -6) (-133) 8-bit Signed number addition What is smallest negative number represented by 8-bit?

Overflow/Underflow Detection C n-1 A n-1 B n-1 S n-1 CnCn OF Examine the MSB bit Bottom line: –P: positive; N: negative –N + N = N –P + P = P –P+N or N+P always fall into the range E.g P cannot be smaller than -128 or bigger than 127 Problem lies in –N+N = P –P+P = N Discarded

Overflow/Underflow Detection C n-1 A n-1 B n-1 S n-1 CnCn OF Discarded

Overflow/Underflow Detection Full Adder AB Cin Cout S S0 A0B0 Full Adder AB Cin Cout S S1 A1B1 Full Adder AB Cin Cout S S2 A2B2 Full Adder AB Cin Cout S S3 A3B3 Carry Overflow/ Underflow n-bit Adder/Subtractor Overflow/ Underflow Cn Cn-1

Overflow/Underflow Example (+72) (+57) (+129) 8-bit Signed number addition (-127) ( -6) (-133) 8-bit Signed number addition Cn-1 = Cn = Cn-1 = Cn =

Parity Circuits To detect single bit error during transmission Parity bit –Even parity: even number for data+parity –Odd parity: odd number for data+parity Single parity bit –Cannot detect 2 bit error –Cannot correct the single bit error SenderReceiver N-bit data Parity bit

Even Parity Generation D0 D1 D2 D3 P_GEN P_GEN = D0  D1  D2  D3 P=1 if odd number of inputs is 1 P=0 if even number of inputs is 1 Sender Receiver 4-bit data Parity bit (P_GEN)

Even Parity Detection Sender Receiver 4-bit data Parity bit (P_GEN) D0 D1 D2 D3 Detection P_GEN P_RECV P_RECV = D0  D1  D2  D3 DETECTION = P_GEN  P_RECV DETECTION=1 if P_GEN  P_RECV

Parity Detection Example D3=0 D2=1 D1=1 D0=1 P_GEN=1 Sender Receiver 4-bit data Parity bit (P_GEN)

Parity Detection Example Sender Receiver 4-bit data Parity bit (P_GEN) D3=0 D2=1 D1=0 D0=1 Detection=1 P_GEN=1 P_RECV= Error occur during transmission