P. 4.1 Digital Technology and Computer Fundamentals Chapter 4 Digital Components

P. 4.2 Objectives n At the end of this chapter, you should be able to: u remember the function and logic circuit of a half adder; u describe the function of a full adder; u draw the logic circuit of a full adder with two half adders and an OR gate; u distinguish the functions of an encoder and a decoder;

P. 4.3 Objectives (Cont’d) u use truth table to define the function of a specific encoder / decoder circuit. u explain the operations of shift register circuits; and u explain the operations of the asynchronous and synchronous counter circuits employing flip-flops.

P. 4.4 References n Thomas C. Bartee, "Digital Computer Fundamentals," sixth edition, McGraw-Hill Publishing Company. n Richard S. Sandige, "Modern Digital Design," McGraw-Hill Publishing Company. n Theodore F. Bogart Jr., "Introduction to Digital Circuits,"” McGraw-Hill Publishing Company.

P. 4.5 Adders n The function of the adder circuits is to perform binary arithmetic. n A major component in the CPU. n All kinds of arithmetic employ adders. n Half adder and full adder.

P. 4.6 Half Adder n It performs half of the one bit addition. n It adds two bits to give a sum and a carry. n It does not consider any carry input. n Therefore it called a half adder.

P. 4.7 Half Adder (Cont’d) n Different conditions for the addition of two binary digits A and B:

P. 4.8 Half Adder (Cont’d) n Carry= A. B Sum=A  B n The logic circuit:

P. 4.9 Full Adder n The full adder circuit is able to complete the full addition process. n There are three inputs, the in carry, C i, and the two binary digits, A and B. n Outputs are sum, S, and an out carry, C o.

P Full Adder (Cont’d) n The function of the full adder circuit.

P Full Adder (Cont’d) n Rearranging:

P Full Adder (Cont’d) n We can build a full adder circuit with two half adders and an OR gate.

P Encoder n The encoder produces a binary output corresponding to an input value. There are 2 n or less input and n output lines in an encoder. n Example: decimal-to-binary encoder.

P Encoder (Cont’d)

P Decoder n The function of a decoder is the reverse process of an encoder. n A decoder converts binary information from n coded inputs to a maximum of 2 n unique outputs. n Example: binary-to-decimal decoder.

P Decoder (Cont’d)

P Counters n Used for the control of sequence and program execution. n Two categories of counters: asynchronous and synchronous. n The asynchronous counters produce the outputs in sequence n The outputs of the synchronous counters are available at the same time.

P Counters (Cont’d) n Counters are made with either J-K or T-type flip-flops.

P Counters (Cont’d) n Q produces one pulse for every two clock pulses input. n The counter counts once for every two clock pulses. n The frequency at Q is half of that at the clock. n Sometimes called a divider. n A J-K flip-flop can be regarded as a divide-by-2 counter.

P Divide-by-16 Ripple (Asynchronous) Counter

P Divide-by-16 Ripple Counter (Cont’d)

P Divide-by-16 Ripple Counter (Cont’d) n Q0 produces one clock pulse for every two input clocks. n At Q3, only one clock pulse is generated for every 16 input clocks. n The output sequence in Q3, Q2, Q1 and Q0, forms the binary numbers from 0 to 15 n It counts the binary numbers.

P Divide-by-16 Ripple Counter (Cont’d) n Propagation delay happens in operations of flip-flops. n Time delay for all output clocks compared with their input clocks. n Outputs are not available at the same time, it is an asynchronous counter.

P Divide-by-16 Ripple Counter (Cont’d) A divide-by-2 n counter can be built with n J-K (or T-type) flip-flops. n Disadvantage: Output clock transitions do not happen at the same time. n The time required for the outputs to be available is equal to n  propagation delay of one flip-flop, not suitable for high-speed circuits

P Divide-by-16 Synchronous Counter n All output clock transitions happen at the same time. n Clocks are connected together. n Input connections are more complicated.

P Divide-by-16 Synchronous Counter (Cont’d)

P Divide-by-16 Synchronous Counter (Cont’d) n FF0 is configured to change output state for every transition of the clock. n FF1 changes output state when the output of FF0 is 1. n When both Q0 and Q1 are at logical 1, the output FF2 changes state after the clock. n FF3 changes state after the clock pulse when all other outputs are at logical 1.

P Divide-by-16 Synchronous Counter (Cont’d) n A divide-by-2 n synchronous counter can be configured using n flip-flops and (n-2) AND gates. n The inputs of the m th flip-flop is connected to the output of an AND gate with its inputs being the outputs of the flip-flop 0 to the (m-1) th flip- flip.

P Shift Registers n Store a vector of binary digits - a simple memory array. n Parallel and serial input methods. n Serial input method shifts the data into the shift register one bit by one bit. n Right-shift: LSB first, MSB last. n Left-shift:MSB first, LSB last. n Parallel input method: stores the data into the register all at a time.

P Shift Registers (Cont’d) n The data in the shift register can be retrieved either in series or in parallel. n Example: 4-bit Left-Shift Register n Built with J-K flip-flops with direct inputs (preset and clear). n Under normal operation, values at the direct inputs are all at logical 1, so that they have no effect on the outputs.

P Shift Registers (Cont’d)

P Shift Registers (Cont’d) n For each flip-flop, the values at their two input terminals are always complemented to each other. n Equivalent to D-type flip-flop configuration. n In figure 4.. The register is initially cleared to 0000 via the clear input by giving a 0 to the clear input line.

P Shift Registers (Cont’d) n The waveform for input data 1101

P Shift Registers (Cont’d) n The data to be stored in the register is n At the end of the forth clock, the data 1011 will be shifted into the register. n Because the data are shifted into the register serially from LSB to MSB, it is a left-shifted register.

P Shift Registers (Cont’d) n At this time, the data can be read from the four Q outputs in parallel. This is called the serial in parallel out operation. n The data can also be read from the Q 3 serially by providing four more clock pulses. Such operation is called serial in serial out operation.

P Shift Registers (Cont’d) n Data can also be entered in parallel using the preset terminals with suitable modifications on the circuit. n In that case, we can operate the register in Parallel in parallel out, and parallel in serial out modes.