Advanced Digital Circuits ECET 146 Week 5 Professor Iskandar Hack ET 221G, Me as I typed this slides

This Week’s Goals Introduction to the concept of Hierarchical Design Techniques Designing a circuit with multiple projects Designing an counter in AHDL

Hierarchical Design Techniques Also called Top-Down Design A design technique that allows a project to be broken into a series of smaller projects Each subdesign is developed and tested separately The overall design is then assembled using either Text Design Techniques or by connecting the subdesigns in the graphical editor (preferred method for this course)

Design a four-bit full adder using Hierarchal Techniques Create a project for One-Bit Half Adder Enter Design Compile Create Default symbol simulate project HA Create a project for One-Bit Full adder Repeat steps from above Create a new project fourbitadd in Graphical Editor Insert a half adder and three full adders, and connect as done in ECET 11 Simulate full design These circuits can be found on pages in ECET 111 textbook

Enter Design for Half Adder Half Adder Simulation of HA

Remember steps from earlier lectures Enter the design using Input Output XOR AND2 Name the pins Save file as ha.gdf Set project to current file Save and Compile (don’t worry about set device or pins since we’re not going to build the subdesign in hardware) Draw Waveforms for Simulation and Simulate

Create Default Symbol This step creates a schematic symbol that can be used in other designs

Default Symbol for Half Adder

Full Adder Repeat process for the Full Adder that you did for the Half Adder

Simulation for Full Adder

Default Symbol for Full Adder

Draw Four-Bit Adder Open Graphical Editor and add the symbols ha and 4-fa’s and connect them as shown with inputs and outputs similar as shown on page 238 in Kleitz Note – All files MUST be in the same directory on the drive!!! Do not put ha, fa and fourbitadder in different directories.

Fourbitadder drawing

Save, Compile, Define Device and Pins After drawing the fourbitadder save it as a new file (fourbitadder.gdf) Set Project to current file Save and Compile Set Device as before to EPM74128SLC84-7 Define input pins and output pins

Pin Assignments

Draw Waveforms for Simulation As before you’ll open the waveform editor and add the nodes from the SNF

Group Inputs and Outputs Group the inputs and outputs to make verification easy

Change Group Values to Verify Circuit Select part of A[] and B[] and assign them random values to see if the circuit actually adds the output

Completed Simulation Waveform Remember that I chose random values for A[0..3] and B[0..3] to test the circuit

Simulate Save the file as fourbitadder.scf and simulate Glitches because of propagation delays

Lab 4 Implement an 8-Bit adder as discussed in this lab Simulate the design Do not Build the circuit, just turn copies of the HA, FA and eightbitadder GDF files and simulation

Introduction to Finite State Machines We will only discuss synchronous Finite State Machines (FSM’s) Synchronous FSM’s will change state only on a rising or falling clock edge The simplest Finite State Machine (FSM ) is a counter Every FSM has an input at a minimum a clock and reset A simple counter the counts from 0 to 5 and repeats has 6 unique states, which I’ll call s0, s1, s2, s3, s4 and s5 A simple counter will change state every clock cycle

A Simple Bubble Graph for Counter

Block Diagram for FSM State Transition Table Clock Reset Other Inputs Current State Next State Outputs

Defining State Machines in AHDL Define Subdesign with Inputs and Outputs as before Add the state machine definition in the variable section Use a table to specify the state transitions Use a 2 nd table to specify the output for each state

AHDL Simple Counter Design Subdesign with I/O specified Tell Altera to set Up State Machine Define how to go from Current State to Next State Define what the outputs are for Each state

Save, Set Project and Compile Repeat steps as done earlier projects Save as projname.tdf Set Project to Current File Save and Compile Define Device and Pins (note Pin 2 is used for clock and Pin 1 for Reset)

Verify Pin Outs in Report File ** PIN/LOCATION/CHIP ASSIGNMENTS ** Actual User Assignments Assignments (if different) Node Name clk count0 count1 count2 reset

Simulate Open Waveform Editor and add nodes from SCF as before The only inputs are reset and clk in this project Take the reset high for ½ clock cycle and use the clock function to define the clock

Simulation Waveform Note the State is Displayed – Very Important for Troubleshooting projects later

Lab 4b Design a counter in AHDL that will count the sequence 0,1,3,4,5,6,7,2,0,1,3,… Simulate the Design and turn in the a copy of the TDF file and Simulation You do not need to build this circuit