© 2003 Xilinx, Inc. All Rights Reserved Answers DSP Design Flow

Answers © 2003 Xilinx, Inc. All Rights Reserved Lab 1: Wrap up Implementation results (including Chipscope Blocks): 304 Slices, ~112 MHz Important to notice: –Global clock buffer is automatically instantiated –Embedded multiplier is used by default in Virtex™-IIP devices. In this lab, the option was turned off in order to use slice-based multipliers Timing constraint should always be used to achieve the performance required –XCF file must be generated manually Remember size to compare with the other flows

Answers © 2003 Xilinx, Inc. All Rights Reserved Module 2: Answers Define the format of the following twos complement binary fraction and calculate the value it represents What format should be used to represent a signal that has: Fill in the table: Using the technique shown, convert the following fractional values… Format = Value = -917 = Format = a) Max value: +1 Min value: -1 Quantized to 12 bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data c) Max value: 278 Min value: -138 Quantized to 11 bit data

Answers © 2003 Xilinx, Inc. All Rights Reserved Lab 2: Solution MAC using embedded multiplier Slice Count: 24 Slices, 1 embedded multiplier Performance: ~244 MHz (2vp4 -7) MAC using slice-based multiplier Slice Count: 69 Slices Performance: ~182 MHz (2vp4 -7) Multiplier Latency - 2

Answers © 2003 Xilinx, Inc. All Rights Reserved Module 3: Answers How many clock cycles per input are required for a fully parallel 12-bit data, 20 tap symmetric filter? –Hardware over-sampling rate = 1 The requirement for a filter is to run at 25 MSPS. A 100 MHz system clock is available on the board. What should the hardware over-sampling rate parameter be set to for 8-bit data? –Hardware over-sampling rate = 100/25 = 4 How many clock cycles per input are necessary to process in serial an 11-bit data, 31 tap symmetric filter? –Hardware over-sampling rate = = 12

Answers © 2003 Xilinx, Inc. All Rights Reserved Lab 3: Solution 365 slices Clock rate: 229 MHz Sample rate: 229/9 = 25.4 MSPS

Answers © 2003 Xilinx, Inc. All Rights Reserved Lab 4: Solution RTL View for Rounding RTL View for Saturation and Rounding

Answers © 2003 Xilinx, Inc. All Rights Reserved Module 4: What Values Do You Expect? Signed Data Truncate and Wrap Signed Data Output Binary point of 3 Total Number of Bits 3 Bottom of Slice offset by 5 from the LSB Number Input Convert Reinterpret Slice

Answers © 2003 Xilinx, Inc. All Rights Reserved Lab 5: Blocks-Based Solution Post-Map Resource Estimates – Slices – 15 – FFs – 16 – LUTs – 28

Answers © 2003 Xilinx, Inc. All Rights Reserved Control Logic Waveform

Answers © 2003 Xilinx, Inc. All Rights Reserved Lab 5: MCode-Based Solution Post-Map Resource Estimates – Slices – 16 – FFs – 16 – LUTs – 28 function done = term_cnt(count) if count == 183 done = true; else done = false; end

Answers © 2003 Xilinx, Inc. All Rights Reserved 44.1 kHz 48 kHz 441 kHz CD format DAT format 7056 kHz Sample Period (GCD) Sample Period Gateway InBlockantiAliasFIRantiAliasFIR1Gateway Out Simulink System Sample Period: Module 6 Exercise: Audio Application Analyze the following sampling rate change system that is commonly found in audio broadcasting studios. Determine the Simulink System Sample period: 1/ / / / / / / / /

Answers © 2003 Xilinx, Inc. All Rights Reserved CE DQ CE2 D CE3 Q CE X y CE CK CE CE2 CE3 System CLK System CE Sample Rate Control Logic Answer: Audio Application CE2 CE3 DAT format DAB format 32 kHz 96 kHz 48 kHz Normalized Sample Times:

Answers © 2003 Xilinx, Inc. All Rights Reserved Answer: Audio Application

Answers © 2003 Xilinx, Inc. All Rights Reserved Q.What would happen if a full precision adder is used in this example? An error will occur as an infinite loop will be created Module 6: Propagation in Loops

Answers © 2003 Xilinx, Inc. All Rights Reserved Lab 6: Solution Slice Count: (with MULT18x18) 89 slices Performance ~204 MHz Slice Count: (Slice-based MULT) 126 slices Performance ~ 208 MHz