Number Systems and Arithmetic or Computers go to elementary school Reading – Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Dr. Leo Porter Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License
What do all those bits mean now? bits ( ) instruction R-formatI-format... data numbertext chars integerfloating point signedunsigned single precisiondouble precision...
Questions About Numbers How do you represent –negative numbers? –fractions? –really large numbers? –really small numbers? How do you –do arithmetic? –identify errors (e.g. overflow)? What is an ALU and what does it look like? –ALU=arithmetic logic unit
Two’s Complement Representation 2’s complement representation of negative numbers –Take the bitwise inverse and add 1 Biggest 4-bit Binary Number: 7 Smallest 4-bit Binary Number: -8 Decimal Two’s Complement Binary Point out negatives, sign bit, how to convert a 2’s complement number
Some Things We Want To Know About Our Number System negation sign extension –+3 => 0011, , – -3 => 1101, ,
Introduction to Binary Numbers Consider a 4-bit binary number Examples of binary arithmetic: = = 6 Binary Decimal Decimal Walk through the add
Can we use that same procedure for adding 2’s complement negative #s as unsigned #s? = = = 1 Selection“Best” Statement AYes – the same procedure applies BYes – the same “procedure” applies but it changes overflow detection CNo – we need a new procedure DNo – we need a new procedure and new hardware to implement it ENone of the above
Overflow Detection So how do we detect overflow for signed arithmetic?
2’s complement? We would like a number system that provides –obvious representation of 0,1,2... – –single value of 0 –equal coverage of positive and negative numbers –easy detection of sign –easy negation uses adder for all addition Two’s complement gives us this.
Arithmetic -- The heart of instruction execution 32 operation result a b ALU Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction
Designing an Arithmetic Logic Unit ALU Control Lines (ALUop)Function –000 And –001 Or –010 Add –110 Subtract –111 Set-on-less-than ALU N N N A B Result Overflow Zero 3 ALUop CarryOut
A One Bit ALU This 1-bit ALU will perform AND, OR, and ADD
A 32-bit ALU 1-bit ALU 32-bit ALU
Subtract – We’d like to implement a means of doing A-B (subtract) but with only minor changes to our hardware. How? 1. Provide an option to use bitwise NOT A 2. Provide an option to use bitwise NOT B 4. Provide an option to use 0 instead of the first CarryIn 5. Provide an option to use 1 instead of the first CarryIn 3. Provide an option to use bitwise A XOR B Explain “Provide an Option”. SelectionChoices A1 alone BBoth 1 and 2 CBoth 3 and 4 DBoth 2 and 5 ENone of the above
Full ALU sign bit (adder output from bit 31) what signals accomplish ADD? Binvert CIn Oper A1 0 2 B C D E NONE OF THE ABOVE ISOMORPHIC
Full ALU sign bit (adder output from bit 31) what signals accomplish OR? Binvert CIn Oper A1 0 0 B C D E NONE OF THE ABOVE ISOMORPHIC Careful – B is correct but E isn’t that far off
Full ALU sign bit (adder output from bit 31) what signals accomplish SUB? Binvert CIn Oper A1 0 2 B C D E NONE OF THE ABOVE Little more intense – can you get this?
Full ALU sign bit (adder output from bit 31) Recall: slt $t0, $t1, $t2 Means: if($t1<$t2) $t0 = 1 else $t0 = 0 Which signals accomplish SLT (assume A is in $t1, B in $t2) (Note that the output “Set” is always passed – what operation ensures it is correct.)? Binvert CIn Oper A1 0 2 B C D E NONE OF THE ABOVE Even harder…. Point out set bit is bit 31 from adder
Full ALU sign bit (adder output from bit 31) what signals accomplish: Binvert CIn Oper add? sub? and? or? beq? slt? For practice
The Disadvantage of Ripple Carry The adder we just built is called a “Ripple Carry Adder” –The carry bit may have to propagate from LSB to MSB –Worst case delay for an N-bit RC adder: 2N-gate delay A0 B0 1-bit ALU Result0 CarryOut0 A1 B1 1-bit ALU Result1 CarryIn1 CarryOut1 A2 B2 1-bit ALU Result2 CarryIn2 A3 B3 1-bit ALU Result3 CarryIn3 CarryOut3 CarryOut2 CarryIn0 CarryIn CarryOut A B The point -> ripple carry adders are slow. Faster addition schemes are possible that accelerate the movement of the carry from one end to the other. Now we’re diving more into CSE140 stuff, let’s step back
MULTIPLY HARDWARE 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Here’s the hardware to do multiply/divide, they USE an adder multiple times.
DIVIDE HARDWARE 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Here’s the hardware to do multiply/divide, they USE an adder multiple times.
You already know a way to write faster code. Let’s say you have code which does: A = B*8. What might you replace that code with to speed up execution (which answer is best) by leveraging faster hardware? SelectionChoices ADo A = B+B+B+B+B+B+B+B BDo A = B sll 3 CDo A = B sra 3 DDo A = B srl 3 ENone of the above Point out a compiler might do this for you.
Floating-Point Numbers Representation of floating point numbers in IEEE 754 standard: single precision 1823 sign exponent: excess 127 binary integer mantissa: sign + magnitude, normalized binary significand w/ hidden integer bit: 1.M (actual exponent is e = E - 127) SE M Need to be able to convert both directions. SelectionChoices A * 2^130 B - 10 C+10 D1.010 * 2^130 ENone of the above Convert the following:
FP Addition Hardware Need to normalize – the key here is this is more complex than Integer Add but not as bad as, say, integer multiply.
Modern Concerns Hardware designers have done an excellent job optimizing multiply/FP hardware, but additions are still faster, than, say multiply. Divides are even slower and have other problems. More complex topics in later lectures will show how multiply/FP/divide may not be on the “critical path” and hence may not hurt performance as much as expected. More recent years have taught us that even “slow” multiply is not nearly as important as cache/memory issues we’ll discuss in later lessons.