WS-RM State Table December 15, 2005. Protocols as State Machines Protocols define the interaction of two or more finite state machines (FSM) Stable Protocols.

Slides:

Advertisements

Similar presentations

Software Engineering - Specifications 1 Specifications Specification document must be clear, complete and correct.

Advertisements

Finite State Machines (FSMs)

PROTOCOL VERIFICATION & PROTOCOL VALIDATION. Protocol Verification Communication Protocols should be checked for correctness, robustness and performance,

Interaction Modeling for Testing We would generate the test cases based on our understanding of the interactions that may happen. The source is, again,

Counters. In class excercise How to implement a “counter”, which will count as 0,3,1,4,5,7,0,3,1,…… Q2Q1Q0D2D1D

TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.

Grey Box testing Tor Stålhane. What is Grey Box testing Grey Box testing is testing done with limited knowledge of the internal of the system. Grey Box.

Chapter 3 Digital Logic Structures

Software system modeling

TCP/IP Protocol Suite 1 Chapter 13 Upon completion you will be able to: Stream Control Transmission Protocol Be able to name and understand the services.

How Computers Work Lecture 6 Page 1 How Computers Work Lecture 6 Finite State Machines.

GA Writing Assessment 5 th Grade – March 2, minutes Use #2 pencil Writing booklet provided.

Model Checking. Used in studying behaviors of reactive systems Typically involves three steps: Create a finite state model (FSM) of the system design.

Heterochronous Dataflow in Ptolemy II Brian K. Vogel EE249 Project Presentation, Dec. 4, 1999.

Overview Finite State Machines

ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)

ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)

Protocol Analysis/Testing Based on Sidhu et al in IEEE TSE 89 and TN 93 Figures from the papers.

Lecture 10 Topics: Sequential circuits Basic concepts Clocks

1 841f06parnas13 Evaluation of Safety Critical Software David L. Parnas, C ACM, June 1990.

Cheng/Dillon-Software Engineering: Formal Methods Model Checking.

Sequential Logic in Verilog

1 COMP541 State Machines Montek Singh Feb 8, 2012.

Modeling Process CSCE 668Set 14: Simulations 2 May be several algorithms (processes) runs on each processor to simulate the desired communication system.

Model Based Conformance Testing for Extensible Internet Protocols Anastasia Tugaenko Scientific Adviser: Nikolay Pakulin, PhD.

Approaching a Problem Where do we start? How do we proceed?

Black Box Testing Techniques Chapter 7. Black Box Testing Techniques Prepared by: Kris C. Calpotura, CoE, MSME, MIT  Introduction Introduction  Equivalence.

Counters. In class excercise How to implement a “counter”, which will count as 0,3,1,4,5,7,0,3,1,…… Q2Q1Q0D2D1D

Chapter 7 The Object-Oriented Approach to Requirements.

Writing System Requirements. Parts of a Requirements Spec. Description of the system –Not your system, yet… Indexed requirements Models of the system.

1 Finite State Machines (FSMs) Now that we understand sequential circuits, we can use them to build: Synchronous (Clocked) Finite State Machines Finite.

ANALYSIS OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.

Registers; State Machines Analysis Section 7-1 Section 5-4.

1 ENGG 1015 Tutorial Three Examples of Finite State Machines Supplementary notes Learning Objectives  Learn about Design of Finite State Machines Ack.:

Copyright 2001, Matt Dwyer, John Hatcliff, and Radu Iosif. The syllabus and all lectures for this course are copyrighted materials and may not be used.

Finite Automata Chapter 1. Automatic Door Example Top View.

Stream Control Transmission Protocol

A sequential logic circuit (a.k.a. state machine) consists of both combinational logic circuit(s) and memory devices (flip flops). The combinational circuits.

1 Specification A broad term that means definition Used at different stages of software development for different purposes Generally, a statement of agreement.

© 2009 Pearson Education, Upper Saddle River, NJ All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Digital Logic Design Dr. Oliver Faust.

CS 5150 Software Engineering Lecture 9 Requirements 3.

Simulation Examples And General Principles Part 2

COMBINATIONAL AND SEQUENTIAL CIRCUITS Guided By: Prof. P. B. Swadas Prepared By: BIRLA VISHVAKARMA MAHAVDYALAYA.

Govt. Engineering College- Gandhinagar. It is all about……  STATE MACHINE.

From requirements to specification Specification is a refinement of requirements Can be included together as Software Requirements Specifications (SRS)

Finite State Machines Mealy machine inputs Outputs next state function

Modeling for Testing Interactions

1.3 Finite State Machines.

UNIT V STATES, STATE GRAPHS, AND TRANSITION TESTING STATE GRAPHS

Finite State Machines Dr K R Bond 2009

Instructor: Alexander Stoytchev

Instructor: Alexander Stoytchev

CSE 370 – Winter Sequential Logic - 1

State Machines Massimo Felici.

Good morning! Today we will be doing some exam/Paper 1 review activities. Please clear off your desks and put away your phones.

COSC 4506/ITEC 3506 Software Engineering

2) For each of the finite state machines above, use the sets derived in part 1) to produce the following: i. a set of sequences that.

Software system modeling

Midterm Review CSE321 B.Ramamurthy 4/13/2019 B.Ramamurthy.

Software design and architecture

Sample Test Questions Please identify the use cases of the system that cover all the behaviors described in the system specification. Please identify.

x/÷ Numbers Year 3-4 – Multiply and divide a multiple of 10

Lecture 18 Logistics Last Lecture Today HW6 due today Midterm 2

UML State Diagrams.

Lecture 4 Sequential units. Registers

CS 501: Software Engineering Fall 1999

Presentation transcript:

WS-RM State Table December 15, 2005

Protocols as State Machines Protocols define the interaction of two or more finite state machines (FSM) Stable Protocols return to base states naturally or as a result of error processing Stable protocols consider that any potential event may occur in any state Each protocol may be represented by a minimum set of states for each state machine needed to describe it

Why State Tables A collection of spec paragraphs is open- ended, but a FSM must be closed Useful to improve clarity of specification –Less ambiguous than words alone –Highlights conditions that may be underspecified

A useful discipline Reliable implementations must consider all potential events and must have a clear transition state to state Provides the means to demonstrate correctness Helps define test cases to demonstrate implementation correctness and robustness

Tables vs Diagrams Tables need only pencil and paper (and eraser?) to create Closure trivial to determine by inspection

What we found The good –The spec is pretty good, only about half of the state/event combinations are unclear or unspecified The bad –We need to work on faults The ugly –Safety of sequence termination is in question