May 17, USB Semiconductor IP How to Integrate USB into Your Design Eric Huang inSilicon Corporation

May 17, Decision Process w Do you need USB 2.0 functionality? w Integration approaches – Standard Product – Integrate Core into Design

May 17, Implementation Choices w Buy a Standard Product – An off-the-shelf chip or part w Make it yourself – Time & resources to develop USB 2.0 w Buy a commercial core – Source USB 2.0 core from Semiconductor IP vendor

May 17, Approaches to USB Integration 1) Buy a Standard Product

May 17, USB Standard Chips Block Diagram USB Standard Chip Your ASIC and Application Logic PHYPHYPHYPHY PHYPHYPHYPHY DMA or RAM MCU or State Machine Fixed Endpoints Application Bus

May 17, USB Standard Product Advantages w Off-the-shelf part for fast implementation w Software configurability of USB endpoints w Basic or sample software included w Feature set is programmable

May 17, USB Standard Product Costs w Not good for high volume production – Several (3x-10x) times the cost of SIP – Higher pin count – Can not shrink die size for cost reduction w May require two microcontrollers in a single design – 1 in the standard chip, 1 in the application w Shifts burden to software w Basic software may require extensive adaptation w USB 2.0 requires more powerful microcontrollers

May 17, Approaches to USB Integration 2) Make It Yourself

May 17, The Design is Coded, I’m Done w Doing the design is easy … – … to guarantee it works in all systems is 10x harder w For risk reduction these factors are more important – Verification – Compliance – Interoperability

May 17, The Design is Coded, I’m Done w Internally developed USB SIP may not guarantee interoperability – Even implemented in silicon several times w Peripherals in production are the only true measurement of interoperability – Millions shipped defines interoperability Continued

May 17, Magnitude of Effort w Many components needed – Core – Test Environment – Verification – Interoperability w For Example – USB 1.1 investment 50 man years – USB 2.0 investment to date 3+ man years

May 17, What Is at Stake? w Design delays – Incomplete product, inadequate support, poor documentation w Product respins – ASIC mask sets cost over $300K – Months of delay w System incompatibility – Product returns, rework w Risk market position and profits w Millions of dollars at risk – High stakes dictate focus on risk reduction

May 17, Approaches to USB Integration 3) Buy a Commercial Core

May 17, What Is USB SIP? w SIP stands for “Semiconductor Intellectual Property” w Digital Synthesizeable design: – RTL Source Code in Verilog or VHDL – Process Independent – Adds the USB functionality to design – Easily integrates into ASIC / ASSP / FPGA

May 17, USB Core Block Diagram Your Integrated ASIC Core PHYPHYPHYPHY PHYPHYPHYPHY DMADMA State Machine Endpoints & Alternates Application Bus Your App Logic Your Integrated ASIC Core PHYPHYPHYPHY PHYPHYPHYPHY DMADMA State Machine Your App Logic

May 17, Why USB SIP? w High volume, low cost solution w Risk reduction with reusable cores w Focus your best resources on new features that differentiate your product w Leverage and use USB SIP from a USB expert – SIP vendors support many customers – Speed your time to market – Keep pace with evolving USB standards – Ensure interoperability in a changing environment

May 17, USB Core Advantages w Endpoint Configurability – Windows programs class drivers to select endpoint alternates – Offers flexibility in the use of the final product w Eliminates the need for a microprocessor w Performance – Throughput – Latency w Easier path to cost reduction: – Include in a system on a chip design – Shrink die size with a USB Core

May 17, USB Core Concerns w Discipline needed in design process w Can not change endpoints after fabrication w Requires commitment in product features w Is the core fully asychronous? w Is the core scannable?

May 17, What Should I Look for in USB SIP?

May 17, Interoperability w Component level – USB core integrates easily to any on-chip bus (proprietary or standard) – USB core connects easily to any standard Phy (UTMI) – USB core uses a standard interface for connecting to any on-chip bus – Independent of process flow or compilation tools w System level – USB peripheral will connect to any USB compliant PC

May 17, Verification and Compliance w Build test vectors for corner cases – Test for abnormal signaling conditions – Test for response to non-compliant activity w Build test vectors for compliance – USB 1.1 – USB 2.0 – Test under minimal loading – Test with many different USB configurations w Update verification suite as standard evolves

May 17, Market Proven w Proven in FPGAs w Proven in Silicon – Proven in standard products – Proven in many processes w USB Plugfest interoperability tested w Core integrated in many designs – Cameras, Printers, Scanners, Modems… w Systems in volume reduction w Leadership and expertise in creating standards – Adapts cores to an evolving standard – Vendor updates cores as the standard changes

May 17, Configurability w Device core implemented in many configurations – Control, Interrupt, Bulk, and Isochronous pipelines exercised extensively – Endpoints implemented in many combinations of interfaces and alternates – Implemented in different processes w Configurable cores save design & test time w Reduces risk

May 17, There’s More to USB SIP Than Just Having a Core w Great test environment w Easy, sensible configurability w Training w Support – Well-documented Cores – Documentation for reuse – Dedicated USB support – Experienced USB development engineers

May 17, Standards Checklist w Proven USB 2.0 Compliance w Proven USB 1.1 Compliance w Standard interface to USB Transceiver (e.g. UTMI) – UTMI for USB 2.0 w Standard interface to an on chip bus (e.g. VCI) w Tool independence

May 17, Questions to Ask w How many times has your USB SIP product been used? w Is USB SIP your main line of business? w Does your USB SIP use standard interfaces? – Does your USB 2.0 core have UTMI? – Does your USB core have a VC interface (VCI)? w Can your USB core interface to any on-chip bus?

May 17, Questions to Ask w What kind of post-sales support do you have? w Are your USB engineers dedicated to USB SIP? w Did you develop your USB SIP in-house? w Do you provide source code? w What kind of test environment do you provide? Continued

May 17, inSilicon The USB SIP Market Leader w Proven in Silicon – Over 100 customers and designs w Interoperability – Millions of units shipped w Completeness – Test Environment, Core, and Software w Support – Expert, focused, available – Configurable - Rapidscript

May 17, inSilicon The USB SIP Market Leader w Verification and Compliance w Standards Based – UTMI for USB 2.0 – VCI to interface to any bus or application – Independent of process, foundry, & tools Continued

May 17, Questions? w w USB 2.0 Device Core w w USB 1.1 OHCI Host w w USB 1.1 Device w w USB 1.1 Hub