Self-replication of complex machines. Cellular Self-Replication The molecular FPGA is used to CREATE the array of cells in the first place, before differentiation.

Slides:

Advertisements

Similar presentations

Day - 3 EL-313: Samar Ansari. INTEGRATED CIRCUITS Integrated Circuit Design Methodology EL-313: Samar Ansari Programmable Logic Programmable Array Logic.

Advertisements

Daniel Mange Towards Robust Bio-Inspired Circuits: The Embryonics Approach ECAL’99, Lausanne September 15, 1999.

Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.

Architecture-Specific Packing for Virtex-5 FPGAs

Implementation Approaches with FPGAs Compile-time reconfiguration (CTR) CTR is a static implementation strategy where each application consists of one.

Committee Members: Annie S. Wu, Jooheung Lee, and Ronald F. DeMara Committee Members: Annie S. Wu, Jooheung Lee, and Ronald F. DeMara Optimizing Dynamic.

Minimizing Clock Skew in FPGAs

Network+ Guide to Networks, Fourth Edition

Zheming CSCE715.  A wireless sensor network (WSN) ◦ Spatially distributed sensors to monitor physical or environmental conditions, and to cooperatively.

Embryonics: A New Methodology for Designing Field-Programmable Gate Arrays with Self-Repair and Self-Replicating Properties Laboratory for Reliable Computing.

SOAR Processing with Field Programmable Gate Arrays Presented by Matthew Scarpino Hoplite Systems LLC.

Lecture 26: Reconfigurable Computing May 11, 2004 ECE 669 Parallel Computer Architecture Reconfigurable Computing.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

CMOL overview ● CMOS / nanowire / MOLecular hybrids ● Uses combination of Micro – Nano – Nano implements regular blocks (ie memory) – CMOS used for logic,

7. Fault Tolerance Through Dynamic or Standby Redundancy 7.6 Reconfiguration in Multiprocessors Focused on permanent and transient faults detection. Three.

LabVIEW Design of Digital Integrated Circuits FPGA IC Implantation.

The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays Steven J.

CS 151 Digital Systems Design Lecture 38 Programmable Logic.

WAN Technologies.

Field Programmable Gate Array (FPGA) Layout An FPGA consists of a large array of Configurable Logic Blocks (CLBs) - typically 1,000 to 8,000 CLBs per chip.

Ontogenetic systems Drawing inspiration from growth and healing processes of living organisms… …and applying them to electronic computing systems Phylogeny.

Dr. Konstantinos Tatas ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction.

Read Only Memory (ROM) Number of words Size of word A block diagram of a ROM consisting of k inputs and n outputs is shown below. The inputs provide the.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Development in hardware – Why? Option: array of custom processing nodes Step 1: analyze the application and extract the component tasks Step 2: design.

Uniform Reconfigurable Processing Module for Design and Manufacturing Integration V. Kirischian, S. Zhelnokov, P.W. Chun, L. Kirischian and V. Geurkov.

Matthew Ziegler CS 851 – Bio-Inspired Computing Evolvable Hardware and the Embryonics Approach.

ECE 465 Introduction to CPLDs and FPGAs Shantanu Dutt ECE Dept. University of Illinois at Chicago Acknowledgement: Extracted from lecture notes of Dr.

High-Level Interconnect Architectures for FPGAs An investigation into network-based interconnect systems for existing and future FPGA architectures Nick.

NIMIA October 2001, Crema, Italy - Vincenzo Piuri, University of Milan, Italy NEURAL NETWORKS FOR SENSORS AND MEASUREMENT SYSTEMS Part II Vincenzo.

PROGRAMMABLE LOGIC DEVICES (PLD)

CPLD (Complex Programmable Logic Device)

J. Christiansen, CERN - EP/MIC

Seattle June 24-26, 2004 NASA/DoD IEEE Conference on Evolvable Hardware Self-Repairing Embryonic Memory Arrays Lucian Prodan Mihai Udrescu Mircea Vladutiu.

Field Programmable Gate Arrays (FPGAs) An Enabling Technology.

Chapter 17 Internetworking: Concepts, Architecture, and Protocols

Basic Sequential Components CT101 – Computing Systems Organization.

“Politehnica” University of Timisoara Course No. 2: Static and Dynamic Configurable Systems (paper by Sanchez, Sipper, Haenni, Beuchat, Stauffer, Uribe)

MAPLD 2005/254C. Papachristou 1 Reconfigurable and Evolvable Hardware Fabric Chris Papachristou, Frank Wolff Robert Ewing Electrical Engineering & Computer.

Task Graph Scheduling for RTR Paper Review By Gregor Scott.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Design Criteria and Proposal for a CBM Trigger/DAQ Hardware Prototype Joachim Gläß Computer Engineering, University of Mannheim Contents –Requirements.

Lecture 12: Reconfigurable Systems II October 20, 2004 ECE 697F Reconfigurable Computing Lecture 12 Reconfigurable Systems II: Exploring Programmable Systems.

Development of Programmable Architecture for Base-Band Processing S. Leung, A. Postula, Univ. of Queensland, Australia A. Hemani, Royal Institute of Tech.,

Section 1  Quickly identify faulty components  Design new, efficient testing methodologies to offset the complexity of FPGA testing as compared to.

“Politehnica” University of Timisoara Course Advisor:  Lucian Prodan Evolvable Systems Web Page:   Teaching  Graduate Courses Summer.

“Politehnica” University of Timisoara Course No. 3: Project E MBRYONICS Evolvable Systems Winter Semester 2010.

Self-Organizing Architectures SOAR 2010 International Conference on Autonomic Computing and Communication, ICAC Washington DC, USA June 7, 2010.

Basic Logic Functions Chapter 2 Subject: Digital System Year: 2009.

Reconfigurable architectures ESE 566. Outline Static and Dynamic Configurable Systems –Static SPYDER, RENCO –Dynamic FIREFLY, BIOWATCH PipeRench: Reconfigurable.

Self-Adaptive Embedded Technologies for Pervasive Computing Architectures Self-Adaptive Networked Entities Concept, Implementations,

1 Advanced Digital Design Reconfigurable Logic by A. Steininger and M. Delvai Vienna University of Technology.

The Third Way: Neither Hardware Nor Software Gordon Brebner Division of Informatics University of Edinburgh.

Dynamic Control of Coding for Progressive Packet Arrivals in DTNs.

Evolving, Adaptable Visual Processing System Simon Fung-Kee-Fung.

EE121 John Wakerly Lecture #15

Ontogenetic hardware Ok, so the Tom Thumb algorithm can self- replicate an arbitrary structure within an FPGA But what kind of structures is it interesting.

LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell.

A Survey of Fault Tolerant Methodologies for FPGA’s Gökhan Kabukcu

3-1 MKE1503/MEE10203 Programmable Electronics Computer Engineering Department Faculty of Electrical and Electronic Universiti Tun Hussein Onn Malaysia.

Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.

Reconfigurable Computing1 Reconfigurable Computing Part II.

VLSI Design Flow The Y-chart consists of three major domains:

Programmable Hardware: Hardware or Software?

Electronics for Physicists

Parallel and Multiprocessor Architectures

We will be studying the architecture of XC3000.

Ontogenetic hardware Ok, so the Tom Thumb algorithm can self-replicate an arbitrary structure within an FPGA But what kind of structures is it interesting.

Electronics for Physicists

In-network computation

Presentation transcript:

Self-replication of complex machines

Cellular Self-Replication The molecular FPGA is used to CREATE the array of cells in the first place, before differentiation can take place (self-replication)

Self-organization So we can make cells appear and disappear at will in a surface of silicon.

Self-organization We can then apply all sorts of nice algorithms: Coordinates 1,1 1,2 2,1 1,3 2,2 3,1 1,4 2,3 3,2 4,1 1,5 2,4 3,3 4,2 2,5 3,4 4,3 3,5 4,4 4,5

Self-organization We can then apply all sorts of nice algorithms: Coordinates Gradients 1,11,2 2,1 1,3 2,2 3,1 1,4 2,3 3,2 4,1 1,5 2,4 3,3 4,2 2,5 3,4 4,3 3,5 4,44,5

Self-organization We can then apply all sorts of nice algorithms: Coordinates Gradients L-Systems 1,11,2 2,1 1,3 2,2 3,1 1,4 2,3 3,2 4,1 1,5 2,4 3,3 4,2 2,5 3,4 4,3 3,5 4,44,5

1,11,2 2,1 1,3 2,2 3,1 1,4 2,3 3,2 4,1 1,5 2,4 3,3 4,2 2,5 3,4 4,3 3,5 4,44,5 Self-organization But all this is (relatively) useless… ABCDE FGHIJ KLMNO PQRST … unless the system can use the algorithms

X X Engineering challenges Connectivity – cellular division AB EF C I D G J M X H K N L OPX F FF

X X Engineering challenges Connectivity – cellular division AB EF C I D G J M X H K N L OPX F FF

X X Engineering challenges Connectivity – cellular division and fault tolerance AB EF C I D G J M X H K N L OPX F FF LX L

X X Engineering challenges Connectivity – cellular division and fault tolerance AB EF C I D G J M X H K N L OPX F FF X L

Embryonics – The BioWatch

MUXTREE Molecule The “molecular” layer of Embryonics is an FPGA

Kill a Molecule

MUXTREE Molecule The molecules are configured and interconnected to realize a cell

MUXTREE Molecule All connections must be re-routed Hardware re-routing is a good option because: The connections are few They rely on fixed, configuration-independent resources (metal lines)

Kill Again (Kill a Cell)

All connections must be re-routed (including those used to compute the coordinates) In reality, we “cheated”, since we assumed that: The organism is one-dimensional It’s possible to route lines through a faulty cell Self-Repair

The mechanism can be extended to two dimensions, by “sacrificing” an entire column whenever a cell dies But it represents a major loss of efficiency Hardware re-routing like in the molecules is not an option, because these connections depend on the configuration and change from one application to the next (different cell sizes, communication patterns, etc.)

S T T ?

The problem of connectivity Connectivity is a major issue, for self-repair but also in general for developmental systems Solutions for specific cases (e.g., RAM) are common, but general ones are very rare (at logic level, i.e., FPGAs) The problem is that, in conventional FPGAs, all the communication paths are part of the configuration of each individual element One solution was proposed in the POEtic project, a EU project that ran from 2001 to It involves the development of a novel FPGA circuit for bio-inspired circuits that exploits a dynamic connection network

The POEtic molecule An industry-level programmable logic element

The POEtic molecule Molecules, through their configuration, can alter their functional structure

Connectivity – The POEtic approach The problem is that, in conventional FPGAs, all the communication paths are part of the configuration of each individual element The POEtic solution = dynamically set-up the communication paths at runtime, using a dedicated, configuration-free routing layer

Connectivity – The POEtic approach In POEtic, molecular connections (gate-to-gate) are realized conventionally and repair can use hardware re- routing. Cellular connections (processor-to-processor) are realized dynamically in the configuration-free routing layer

S T T

Next week We can design complex digital circuits that self- replicate These circuits can self-repair And they can re-route their connection network dynamically when needed But what ARE these circuits? In the BioWatch, they were hand-designed processors. Do we need to hand-design every single circuit, or can we find a processor architecture ideally suited to this kind of non-conventional systems?