Performance Challenges of Future DRAM´s SINANO WS, Munich, Sept. 14th, 2007 M. Goldbach / J. Faul

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 2 Content Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 3 Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 4 MOS Transistor Scaling (1974 to present): Note: Scaling refers to gate half Pitch in nm Introduction I Pitch Half Pitch 250  180  130  90  65  45  32  x 0.7x HP logic HP logic: Speed & area driven DRAM: Area & speed driven  more nodes, however smaller steps

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 5 Introduction II ITRS Roadmap 2001: Scaling continues, however, logic scaling slowed down to 3 yrs cycle

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 6 Scaling history for - power-supply voltage V dd - threshold voltage V t - gate oxide thickness t ox  Vdd, Vt and tox saturate! Key Question: Are we approaching the limit of silicon scaling!? Introduction III

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 7 Ref. 1 Introduction IV Power Consumption: Both, passive and active power density increase 8” hot plate at 1500W Reason: Demand for ever increasing performances

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 8 Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 9 DRAM´s are offered in various densities & architectures: Synchronous DRAM: Data, commands, and addresses synchronized with clock Single data rate (SDR) Double data rate (DDR) Double data rate II (DDR II) DRAM Challenges I (Architectures) Vdd Vss Vddq Vssq Clock Adresses Data (DQ) Commands DRAMDRAM Simplified Block Diagram DRAM Clock Data SDR Data DDR Data DDR II (double freq) Commands DDRII

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 10 DRAM Challenges II (Speed Classes) For DDR, data rate 2x clock frequency (both graphics and main memory) Ref. 2

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 11 DRAM Challenges III (Array Access) Array Access: tAA ~ Tpd Higher densities: More speed critical speed depends on parasitics tAA: Array Access Time Tpd: Propagation delay Ref. 2

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 12 DRAM Challenges IV (General Remarks) Strong Interaction Array / Support Device Design - Defect Treatment Required for long data retention, however, limited doping activation - Structuring Structure both, dense array and logic circuits in same steps - Density / Aspect ratios Driven by very dense cell areas - Low leakage requirements Junction leakage < 1fA per node in array Array transistor: < 1fA to ensure data retention Support transistors:Ioff ~10pA/µm (high speed logic ~100nA/µm) Low Complexity & overall costs

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 13 Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 14 Array Device Scaling I (Asymmetric Device) Asymmetric Device: Low Node leakage & low Ioff by asymmetric well doping Forward Reverse Reverse: Node Forward: Bit Line (BL) - contact DRAM cell schematics Asymmetric cell device Ref. 5

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 15 Array Device Scaling II (EUD Device) X-section along device (perpendicular WL) X-section width device (parallel WL) All major DRAM companies convert from planar to 3D devices in the 60-90nm nodes Example: Qimonda´s Extended U-shape device (EUD) Ref. 3

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 16 Transfer Characteristics Side gate device Impact Data retention Characteristics Target Vnwll Introduction of EUD for node field reduction (no current gain expected) Current modification by side gate Array Device Scaling III (EUD Device) Ref. 3

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 17 Array Device Scaling IV (FinFet in Array) Fig.12: Measured FinFET I  -V  characteristics of the 90nm demonstrator for different p-well voltage (V  ). X-section along device (perpendicular WL) X-section width device (parallel WL) Motivation for FinFet: Slope of 85°C achieved Ids of ~ 30µA achieved no Body effect No body effect Potential Future: FinFet in array Ref. 4

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 18 Array Device Scaling V (Array Path) Ref. 2

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 19 Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 20 Support Device Scaling I (History) DRAM Support Device Scaling: L poly scales by ~0.5x every 3 years DRAM support transistors longer than high speed logic devices but comparable to low standby power Since ~ 2006: L poly (pf) = L poly (nf) (Dual gate work function processes) Off current constraints: Logic L poly scaling slows down L poly scaling drives scaling of other properties as well DRAM Ref. 5

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 21 Support Device Scaling II (Topics & Issues) Scaling Topics Issues Ref. 2

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 22 Support Device Scaling III (Gox scaling) Gate Oxide Scaling: Gate Oxide Leakage: I g (t ox ) = A 0 exp(–B 0 t ox ) Direct tunnelling thru dielectric Ig(nf) ~ 1.5 dec higher than Ig(pf) (Reason: Hole vs. electron tunneling) Ig / tox ~ 1dec / 2 Angstrom For tox  2.5nm Ig uncritical (Ig < 10pA/µm²) Between 2 < tox < 2.5nm Ig needs to be considered Below 2nm: High k gate dielectrics might be employed (Eqivalent oxide thickness (EOT)) Ref. 6

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 23 Support Device Scaling IV (Scaling Path) Ref. 2

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 24 Introduction DRAM Challenges Array Device Scaling Support Device Scaling Conclusion

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 25 Scaling of Si technology not yet reached  will continue down below 30nm ground rules Unlike logic, DRAM support device design obey array driven limitations (e.g. doping activation, structuring, low leakage requirements) Array device scaling path: conventional  asymmetric doping  3D structures Support device scaling path: conventional  adaptions (e.g. stress, high k)  3D structures Conclusion

For internal use only · Copyright © Qimonda AG 2006 · All rights reserved.Qimonda · M. Goldbach · Month Date, Year · Page 26 1.“Silicon CMOS devices beyond scaling”, W. Hänsch et al., IBM J. of Res. and Dev. 50, DRAM short course, VLSI 2007, by S. Hong. 3.“A 58nm Trench DRAM Technology”, T. Tran et al., IEDM “DRAM Scaling Roadmap to 40nm”, W. Müller et al., IEDM “Transistor Challenges – A DRAM Perspective”, J. Faul et al., NIM in Phys. Res. B 237 (2005) “Ultra Low Power SRAM technology”, R.W. Mann et al., IBM J. of Res. and Dev. 47, References

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