Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005.

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Presentation transcript:

Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005

Topic Definitions Visual Introduction of VHDL using EVITA ( Getting started with Xilinx ISE Tool Simulation of VHDL Models with Moldelsim

Definition of an HDL Def: A high level programming language used to model hardware. – special hardware related constructs – digital (now) and analog (near future) – models used for documentation, simulation, synthesis, and test generation – have been extended to the system design level

Language Semantics Semantics: what is the meaning of a language construct? HDLs have different semantics for different applications: – Simulation – Synthesis – Test In this course we will be concerned with simulation and synthesis semantics.

VHDL VHDL = VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Program DOD began development in 1983 – design exchange among VHSIC contractors – document parts with long functional life IEEE Standardization – Standardization process began in 1985 – IEEE Standard 1076 in 1987 – Updated in 1993

Significance of VHDL VHDL provides a text based approach to structured hardware modeling and design. Analogous to high level software languages such as PASCAL, C, C++, and JAVA. An important tool in managing the complexity of VLSI systems.

Why Use VHDL? Reason #1: it allows textual design representation Reason #2: Ability to model at different levels of abstraction

Abstraction Levels SYSTEM CHIP REGISTER GATE CIRCUIT SILICON

SILICON LEVEL

CIRCUIT LEVEL N D P S V+V+ G V in V out D G S Inverter

GATE LEVEL S Q Q R Q QR S Flip Flop

REGISTER LEVEL Select REG INC MUX CLK B CLK A

CHIP LEVEL µ RAM Par. Port USART Int. Con. P

SYSTEM LEVEL A/B Computer IMU C/D RADAR

– VHDL Provides total modeling capability at the gate level, register level, and chip level. – It can also be used in many applications at the: system level circuit level Switch level (gate-circuit hybrid)

VHDL supports very naturally the Design Decomposition process. Structural Decomposition behavioral model Reason #3: Design Decomposition

VHDL can be used to validate design at a high level, thus detecting errors early in the design process Important, because finding errors later is expensive Reason #4: Design Validation