irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types of 3D-MAPS design

IRFU - IPHC /10/2009 Ecole microélectronique de l'IN2P3 Using 3DIT to improve MAPS performances 3DIT are expected to be particularly beneficial for MAPS : CCombine different fabrication processes RResorb most limitations specific to 2D MAPS Split signal collection and processing functionalities, use best suited technology for each Tier : TTier-1: charge collection system  Epitaxy (depleted or not)  ultra thin layer  X 0  TTier-2: analogue signal processing  analogue, low I leak, process (number of metal layers) TTier-3: mixed and digital signal processing TTier-4: data formatting (electro-optical conversion ?) digital process (number of metal layers) feature size  fast laser driver, etc. Analog Readout Circuit Diode Pixel Controller, A/D conversion Pixel Controller, CDS Digital Analog Sensor ~< 50 µm Analog Readout Circuit Diode ~ 20 µm Analog Readout Circuit Diode Analog Readout Circuit Diode TSV 2D - MAPS 3D - MAPS Sensor tier = MAPS  integration 1st level amplification µm Radiation hard Cluster  S/N

IRFU - IPHC /10/2009 Ecole microélectronique de l'IN2P3 High resistivity sensitive volume  faster charge collection Exploration of a VDSM technology with depleted (partially ~30 µm) substrate:  Project "LePix" driven by CERN for SLHC trackers (attractive for CBM, ILC and CLIC Vx Det.) Exploration of a technology with high resistivity thin epitaxial layer  XFAB 0.6 µm techno: ~15 µm EPI (  ~ O(10 3 ) .cm), Vdd = 5 V (MIMOSA25)  Benefit from the need of industry for improvement of the photo-sensing elements embedded into CMOS chip For comparison: standard CMOS technology, low resistivity P-epi high resistivity P-epi: size of depletion zone size is comparable to the P-epi thickness! TCAD Simulation (by A. DOROKHOV) 15 µm high resistivity EPI compared to 15 µm standard EPI

IRFU - IPHC /10/2009 Ecole microélectronique de l'IN2P3 Landau MP (in electrons) versus cluster size 0 n eq /cm² 0.3 x n eq /cm² 1.3 x n eq /cm² 3 x n eq /cm² MIMOSA25 in a high resistivity epitaxial layer 20 μm pitch, + 20°C, self-bias 4.5 V, 160 μs read-out time Fluence ~ (0.3 / 1.3 / 3·)10 13 n eq /cm 2  Tolerance improved by > 1 order of mag. Need to confirm  det (uniformity !) with beam tests 16x96 Pitch 20µm MIMOSA25 To compare: «standard» non-depleted EPI substrate: MIMOSA15 Pitch=20µm, before and after 5.8x10 12 n eq /cm 2 saturation -> >90 % of charge is collected is 3 pixels -> very low charge spread for depleted substrate

IRFU - IPHC /10/2009 Ecole microélectronique de l'IN2P3 IPHC 3D-MAPS: Self Triggering Pixel Strip-like Tracker (STriPSeT) Combine Tezzaron/Chartered 2-tiers process with XFAB high resistivity EPI process  Tier-1: XFAB, 15 µm depleted epitaxy  ultra thin sensor!!! Depleted  Fast charge collection (~5ns)  should be radiation tolerant For small pitch, charge contained in less than two pixels Sufficient (rather good) S/N ratio defined by the first stage “charge amplification” ( >x10) by capacitive coupling to the second stage  Tier-2: Shaperless front-end: (Pavia + Bergamo) Single stage, high gain, folded cascode based charge amplifier, with a current source in the feedback loop  Shaping time of ~200 ns very convenient: good time resolution Low offset, continuous discriminator  Tier-3: Digital: Data driven (self-triggering), sparsified binary readout, X and Y projection of hit pixels pattern Matrix 256x256  2 µs readout time Tier-1Tier-2Tier-3 Cd~10fF G~1 Cc=100fF Cf~10fF  off <10 mV Digital RD Vth Ziptronix (Direct Bond Interconnect, DBI®*) Tezzaron (metal-metal (Cu) thermocompression)  DBI® – Direct Bond Interconnect, low temperature CMOS compatible direct oxide bonding with scalable interconnect for highest density 3D interconnections ( 10 8 /cm² Possible) W. DULINSKI, A. DOROKHOV, F. MOREL, G. BERTOLONE, X. WEI, … 20 µm Tier 2

IRFU - IPHC /10/2009 Ecole microélectronique de l'IN2P3 IPHC 3D-MAPS Delayed R.O. Architecture for the ILC Vertex Detector  Try 3D architecture based on small pixel pitch, motivated by : Single point resolution < 3 μm with binary output Probability of > 1 hit per train << 10 %  12 μm pitch :  sp ~ 2.5 μm Probability of > 1 hit/train < 5 %  Split signal collection and processing functionalities : Tier-1: A: sensing diode & amplifier, B: shaper & discriminator Tier-2: time stamp (5 bits) + overflow bit & delayed readout  Architecture prepares for 3-Tier perspectives : 12 µm ~1 ms ~200 ms AcquisitionReadout Y. FU, A. BROGNA, A. DOROKHOV, C. COLLEDANI, C. HU, … Detection diode or Q injection Amplifier NMOS only Amp.+Shaper Discriminator Hit identification 12 µm 24 µm 5 bits (7?) Time Stamp 2nd hit flag Delayed Readout Tier 1Tier 2 A B future + Detection diode & Amp ASD TS & R.O. 12 µm

IRFU - IPHC /10/2009 Ecole microélectronique de l'IN2P3 IRFU & IPHC 3D-MAPS: RSBPix FAST R.O. architecture aiming to minimise power consumption  Subdivide sensitive area in ”small” matrices running INDIVIDUALLY in rolling shutter mode  Adapt the number of raws to required frame r.o. time  few µs r.o. time may be reached (???)  Planned also to connect this 2 tier circuit to XFAB detector tier Building Blocks: PLL, 8b/10b, Bias DAC, Pre-Amplifier, Buffer…. Tier-1: NMOS only Tier - 2 Digital Memory and Digital Readout Discriminator DREADLATCH_D Y. DEGERLI, W. DULINSKI, … (Tier-1) 20µm