NetStaQ ADMA-100 Breaking the Bottlenecks By Curtis E. Stevens Don Doan.

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Presentation transcript:

NetStaQ ADMA-100 Breaking the Bottlenecks By Curtis E. Stevens Don Doan

31-JUL-01 Pacific Digital Corporation Slide 2 Agenda Introduction to ADMA Performance Statistics

31-JUL-01 Pacific Digital Corporation Slide 3 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 4 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 5 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 6 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 7 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 8 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 9 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 10 Drive dead time Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 11 Drive dead time Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 12 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 13 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 14 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 15 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 16 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 17 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 18 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 19 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 20 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 21 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 22 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 23 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 24 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 25 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 26 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 27 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 28 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 29 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 30 Legacy Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 31 Legacy Transfer Statistics Legacy Transfer Statistics Ultra DMA data transfer 8 I/O’s per command –Includes 7 I/O’s for storing the command –Includes 1 I/O to read the status register in the interrupt Additional I/O’s to setup DMA controller 1 Interrupt per command

31-JUL-01 Pacific Digital Corporation Slide 32 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 33 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 34 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 35 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 36 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 37 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 38 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 39 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 40 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 41 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 42 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 43 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 44 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 45 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 46 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 47 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 48 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 49 ADMA Command & Interrupt Flow

31-JUL-01 Pacific Digital Corporation Slide 50 ADMA Transfer Statistics Ultra DMA data transfer No I/O –ADMA registers are memory mapped –ADMA uses normal PCI memory reads and writes to retrieve commands 1 Interrupt per group of I/O requests –Commands that complete while an ADMA interrupt is processed will not generate an additional interrupt

31-JUL-01 Pacific Digital Corporation Slide 51 ADMA Command Chains

31-JUL-01 Pacific Digital Corporation Slide 52 ADMA Block Diagram

31-JUL-01 Pacific Digital Corporation Slide 53 Performance Statistics

31-JUL-01 Pacific Digital Corporation Slide 54 Test Conditions System (Micron) –500Mhz P3 –192MB RAM –NT 4.0 SP6 –Intel Chipset –33Mhz PCI slot on a 66Mhz bus –Micron Northbridge Iometer –Fileserver access pattern –100% Random, 80% Reads, 60% 4k blocks (remainder spread from 512 bytes to 64kbytes) Process –Boot using motherboard controller (same drive for all tests) –UDMA-100 card has for drives attached –ADMA card is in the same slot using the same 4 drives

31-JUL-01 Pacific Digital Corporation Slide 55 File Server Access Pattern Ultra-100 controller using drives that support queueing. The Ultra-100 controller does not using the queing capability of the drive.

31-JUL-01 Pacific Digital Corporation Slide 56 File Server Access Pattern Ultra-100 controller using drives that do not support queueing.

31-JUL-01 Pacific Digital Corporation Slide 57 File Server Access Pattern ADMA controller using drive queing capability

31-JUL-01 Pacific Digital Corporation Slide 58 File Server Access Pattern Overlay of Ultra-100 controller using drives that support queing with ADMA controller using queued capability. The Ultra-100 controller does not using the queing capability of the drive.

31-JUL-01 Pacific Digital Corporation Slide 59 Any Questions