Universal Reconfigurable Processing Platform for Space Presented by Dorian Seagrave Gordonicus LLC

MAPLD 2009 Gordonicus LLC2 Introduction An increasing number of spacecraft system engineers and scientists are demanding: More processing power Flexible architecture Standard / COTS communication interfaces Multiple Mission Modes / Reconfigurability Small form factor Mission hardware reuse Low power High speed SERDES High Reliability

MAPLD 2009 Gordonicus LLC3 Features STS125 Mission Aeroflex LEON3FT UT699 Aeroflex LEON3FT UT699 This hardware platform provides these needs by combining: Reconfigurable State-of-the-Art High Speed Data Processing Capabilities A Rad Hard LEON3FT Processor 1 Gbyte protected SDRAM No blind and buried vias Flight board meets IPC 6012 Class 3 Addition of 1553 Addition of 100 Mb Ethernet Addition of 200 Mb Spacewire routers Addition of COTs Interfaces: cPCI (33MHz) & High Speed SERDES on P2

MAPLD 2009 Gordonicus LLC4 LEON3FT Processing Applications Guidance, Navigation and Control (GNC) Control and Data Handling (CDH) Xilinx Monitoring and Reconfiguration

MAPLD 2009 Gordonicus LLC5 Xilinx Processing Applications High Speed DSP Algorithm Processing Image Processing Pose Estimation Algorithms Communications / Radio Data Encryption / Decryption Waveform Processing Instrument Data Validation and Compression Application Reconfigurable While in Flight

MAPLD 2009 Gordonicus LLC6 SPECIFICATIONS 5 PROCESSORS LEON3FT ASIC AeroFlex UT699 SPARC TM V8/LEON 3FT 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg 4 x 350 MHz PowerPC™ 405 Heritage Implementation Dual Xilinx QV4 FX60 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) STANDARD I/O INTERFACES 10 SPACEWIRE PORTS Up to 200Mbps (Configurable) Supports Cross stapping Multiple configurations CompactPCI 32 Bit, 33MHz Master and Slave Mode Supported PCI 2.2 Compliant NASA Hypertronics connectors Mil-Std-1553 A/B Mil-Std-1553 BC/RT/MT Based on the Actel Core1553 IP CONSOLE PORT LEON3FT UART Rate configurable FRONT PANEL DEVELOPMENT / DEBUG PORTS DEVELOPMENT LEON3FT 10T/100 Ethernet port Xilinx 10T/100 Ethernet port DEBUG LEON Debug Serial Port RTAX Debug Serial Port Xilinx Debug Serial Port JTAG MEMORY 1 GByte SDRAM Reed Solomon Protected corrects for 2 nibble upsets 8 Gbit FLASH stored in two banks 8 Gbit SDRAM 2Gbits per PPC405 2 MBbyte SRAM Protected (Self Scrubbing) 32 KByte PROM CONFIGURABLE I/O 10 RS422/LVDS Transmit Ports Xilinx configured (Quad redundant) 10 RS422/LVDS Receive Ports Xilinx configured (Quad redundant) 39 Xilinx Backplane I/O 12 Actel I/O 2 LEON GPIO 2 Backplane Spacewire Backplane Ethernet SMALL SIZE DIMENSIONS Standard 3U cPCI Single slot front panel configuration supports: 4 SpaceWire, 1553 A/B, Console port and Debug. Dual slot front panel configuration supports additional SpaceWire ports. LOW POWER LEON3FT 2.5Volt Core Xilinx 1.2Volt Core

MAPLD 2009 Gordonicus LLC7 LEON3FT PROCESSOR & MEMORY LEON 3FT AeroFlex UT699 SPARC TM V8 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV- cm2/mg MEMORY 1GByte SDRAM Reed Solomon Protected corrects for 2 nibble upsets 8GByte FLASH Stored in two banks 2MBbyte SRAM Protected (Self Scrubbing) 32KByte PROM

MAPLD 2009 Gordonicus LLC8 LEON3FT PROCESSOR & MEMORY LEON3FT Aeroflex UT699 2MByte SRAM (Internal EDAC ) 32KB PROM 1GByte SDRAM (Reed Solomon) 4GByte FLASH Actel RTAX TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg 52.8 MIPS 4GByte FLASH

MAPLD 2009 Gordonicus LLC9 Xilinx QV4 FX60 FPGAs & MEMORY Quad redundant or independent PPC processing Mixed operating systems Partial or Full reconfiguration CONFIGURABLE LOGIC per FX60 Logic Cells: 56,880 Slices: 25,880 Distributed RAM: 395kb XtremeDSP Slices: 128 Block RAM: 4,176Kb EMBEDDED PowerPC 405  350 MHz operation  16 KB instruction cache  16 KB data cache  32 bit RISC processors  700+ DMIPS  TID: 250 krad (Si)  SEL Immune >110 MeV-cm2/mg  SEFI: 1.5E-6 Upsets/device/day (GEO) MEMORY 8Gbit SDRAM  2Gbits per PPC405

MAPLD 2009 Gordonicus LLC10 Xilinx QV4 FX60 PPC 405 PPC 405 Xilinx QV4 FX60 XILINX PPC405 PROCESSORS & MEMORY PPC MByte SDRAM 200Mbps SpaceWire(4) Dual Xilinx QV4 FX60 PPC DMIPs TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) 512MByte SDRAM 512MByte SDRAM 512MByte SDRAM LEON3FT Aeroflex UT699 Based on Heritage Architecture Implementation

MAPLD 2009 Gordonicus LLC11 Xilinx DSP Processing Architecture PPC1 PPC3 PPC0 PPC2 4 Designs = Quad Redundant or Single Strand 2 Designs = 1 Design per Xilinx 1 Design TMRed using both Xilinx Flexible Design Options : Node Interconnections

MAPLD 2009 Gordonicus LLC12 Xilinx Reconfiguration A Singe Node can be reconfigured with PPC1 PPC3 PPC0 PPC2 Bottom Xilinx QV4 FX60 Top Xilinx QV4 FX60 Xilinx Resources consist of 4 nodes. Node = PPC + surrounding FPGA fabric. Control Logic SDRAM SelectMap PPC Operating system PPC application code or Xilinx fabric reconfiguration WITHOUT disruption to the other nodes FLASH

MAPLD 2009 Gordonicus LLC13 STANDARD INTERFACES CompactPCI Console Port Async UART 1553 SpaceWire

MAPLD 2009 Gordonicus LLC14 CompactPCI MIL-STD-1553 A/B LEON3FT Console Port

MAPLD 2009 Gordonicus LLC15 SpaceWire Ports LEON3FT SpW Router 5 Port SpW Router 5 Port RTAX 200Mbps Configurable 200/100/50 Mbps 200Mbps Front Panel Conn. Thru-hole Jumpers FRONT PANELFRONT PANEL CPCIP2CPCIP2 Xilinx 200Mbps 10 Front Panel 4 Backplane 2 Backplane via Jumpers 200Mbps Configurable

MAPLD 2009 Gordonicus LLC16 Configurable I/O What if my instrument interface is not SpaceWire? What if I need a custom interface on the backplane? ie: I2C What if I forgot to add a control line to a device?

MAPLD 2009 Gordonicus LLC17 LVDS OR RS User Defined I/O LEON3FT FRONT PANELFRONT PANEL CPCIP2CPCIP2 Xilinx 39 User Defined I/O LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 LVDS OR RS422 Sync / Async Serial IF I2C 1 Wire Protocol 10 Bi-Dir User Defined I/O 2 GPIO ACTEL 12 User Defined I/O

MAPLD 2009 Gordonicus LLC18 Development & Debug Ports  LEON 10T/100 Ethernet MII Interface (FRONT Panel or Backplane)  Xilinx 10T/100 Ethernet MII Interface (FRONT Panel or Backplane)  LEON and Xilinx Ethernet ports can be connected  LEON Dedicated Debug Port (DSU)  Xilinx I/O to be used as serial ports  Xilinx JTAG  LEON JTAG  ACTEL JTAG All Debug / Development ports are accessible from the front panel. Facilitates Hardware Reuse GSE reconfiguration without opening the box

MAPLD 2009 Gordonicus LLC19 RTAX 2000 CONFIGURATIONS CG624 Package Supports ALDEC RTAX development Suite. Flexible architecture using Gaisler/Aeroflex Cores

MAPLD 2009 Gordonicus LLC20

MAPLD 2009 Gordonicus LLC21 Availability Contact Aeroflex Colorado Springs

MAPLD 2009 Gordonicus LLC22 Next Implementation LEON3FT or RTAX 12 MBytes EEPROM Dual SpW Ports 16 GBytes FLASH 1 GByte SDRAM 16 MBytes SRAM U cPCI

Gordonicus LLC Hardware Gordon Seagrave  Dorian Seagrave  Software Peter Cavendar  John Gemmill  MAPLD 2009 Gordonicus LLC23