Datapath Architecture Department of Computer Science Southern Illinois University Edwardsville Fall, 2015 Dr. Hiroshi Fujinoki DatapathArchitecture/001 CS 312 Computer Organization and Architecture

Processor DatapathArchitecture/002 What is “datapath”? Memory Instructions (Machine Code) Datapath Datapath: The way instructions are being executed inside a processor CS 312 Computer Organization and Architecture

DatapathArchitecture/003 The four datapath architectures we are going to review in this Chapter (Chapter 3) The two datapath architectures We are going to review in Chapter 8. Six different datapath architectures (1) General-Purpose CISC/special-purpose RISC Processors: (2) Super Computers/Mainframes:  Scalar Processors  Pipeline Processors  Super-Scalar Processors (i8086) (i80486)  Super-Pipeline Processors (i80586 – P54)  Vector Processors  VLIW Processors CS 312 Computer Organization and Architecture

DatapathArchitecture/ Scalar Datapath Processors Processor IFIDEXME WB Datapath The datapath includes the five circuit units All five units are implemented as single monolithic unit When an instruction is being executed, no other instruction can enter the datapath IF: Instruction FetchID: Instruction DecodeEX: Execution ME: Memory access WB: Write Back to registers CS 312 Computer Organization and Architecture

IF IDEXME WB Clock Cycles IF IDEXME WB IF IDEXME WB DatapathArchitecture/005 CPI = Scalar Datapath Processors (continued) Representative processors in this generation i4004, i8080, i8086, i80816, Z80, MC68000 CS 312 Computer Organization and Architecture

DatapathArchitecture/ Pipeline Datapath Processors Processor All five units are implemented as independent units When an instruction is completed in a unit, the instruction can be forwarded to the next unit All five units can be occupied by different instructions IFID EX ME WB Datapath CS 312 Computer Organization and Architecture

Representative processors in this generation i80386, i40846, MC68040, …. IF IDEXME WB IF IDEXME WB Clock Cycles IF IDEXME WB IF IDEXME WB DatapathArchitecture/007 CPI =2.0 8 cycles / 4 instructions 2. Pipeline Datapath Processors (continued) CPI for these only for these four instructions CS 312 Computer Organization and Architecture

DatapathArchitecture/ Super-Scalar Datapath Processors Processor IFIDEXME WB Datapath #1 Multiple Scalar Datapath IFIDEXME WB Datapath #2 CS 312 Computer Organization and Architecture

IF IDEXME WB Clock Cycles IF IDEXME WB IF IDEXME WB IF IDEXME WB IF IDEXME WB IF IDEXME WB DatapathArchitecture/009 CPI = cycles / 6 instructions 3. Super-Scalar Datapath Processors (continued) CS 312 Computer Organization and Architecture

DatapathArchitecture/ Super-Pipeline Datapath Processors Processor A combination of super-scalar and pipeline IFID EX ME WB Datapath #1 IFID EX ME WB Datapath #2 CS 312 Computer Organization and Architecture

IF IDEXME WB IF IDEXME WB Clock Cycles IF IDEXME WB IF IDEXME WB IF IDEXME WB IF IDEXME WB DatapathArchitecture/011 CPI = cycles / 6 instructions 4. Super-Pipeline Datapath Processors (continued) Representative processors in this generation Pentiums (54, P55C), MIPS R10000, …. CPI for these only for these six instructions CS 312 Computer Organization and Architecture

Representative processors in this generation C-90 and Y-MP (Cray), VAX 9000 (Digital), … Clock Cycles EX 2 EX 3 EX 4 EX 5 EX 6 EX 2 EX 3 EX 4 EX 5 EX 2 EX 3 EX 4 IF IDEX 1 ME WB IF IDEX 1 ME WB IF IDEX 1 ME WB DatapathArchitecture/ Vector Datapath Processors (continued) CS 312 Computer Organization and Architecture

DatapathArchitecture/013 Processor An extension of scalar datapath architecture Multiple execution units IFIDME WB Datapath EX 1 EX 2 EX 3 EX 4 EX 5 CS 312 Computer Organization and Architecture 6. VLIW Datapath Processors (continued)

DatapathArchitecture/014 Each instruction has to have multiple operations in it OP EX 1 OP EX 2 P 11 P 12 P 21 P 22          256 bits in Transmeta Crusoe TM8000 Operator 1 Operator 2 OP EX 5 P 52 P 51 Operator 5 Each operator corresponds to an instruction in scalar machine CS 312 Computer Organization and Architecture 6. VLIW Datapath Processors (continued)

Representative processors in this generation TI TMS320C6200, Philips TM1000, Transmeta Crusoe, … EX 2 EX 3 EX 4 EX 5 EX 6 EX 2 EX 3 EX 4 EX 5 EX 2 EX 3 EX 4 IF IDEX 1 ME WB IF IDEX 1 ME WB IF IDEX 1 ME WB DatapathArchitecture/015 CS 312 Computer Organization and Architecture 6. VLIW Datapath Processors (continued)

EX 2 EX 3 EX 4 EX 5 EX 6 EX 2 EX 3 EX 4 EX 5 EX 2 EX 3 EX 4 IF IDEX 1 ME WB IF IDEX 1 ME WB IF IDEX 1 ME WB DatapathArchitecture/ VLIW Datapath Processors (continued) Processor resources are very efficiently used Only if most of the execution units are used Who should make sure this? VLIW can be pipelined …. Very low CPI (< 1.0) possible CS 312 Computer Organization and Architecture