Five Components of a Computer CPU Main Memory Five Components of a Computer Output Devices Input Secondary display screen, printer keyboard, mouse harddisks, floppy disks, tapes, CD-ROMs CPU - Central Processing Unit fetches and follows a set of simple instructions Main Memory stores the executing program and its data in RAM ( random access memory ) Secondary Memory stores permanent records ( files )

Two Principal Microcomputer System Components Hardware Software Hardware: Architecture of a computer - general layout of major Components Microprocessor (CPU) I/O System Memory System BUS Random Access Memory (RAM) Dynamic, Static Cache, Flash Memory Read Only Memory (ROM) 8088/8086 80286, 80386 80486, Pentium Printer, Mouse, DVD Floppy/Hard Disk CD, USB, keyboard Monitor, Tape Backup

System bus (data, address & control signals) System Block Diagram Crystal oscillator Timing circuitry (counters dividing to lower frequencies) P + associated logic circuitry: Bus controller Bus drivers Coprocessor ROM (Read Only Memory) (start-up program) RAM (Random Access Memory) DRAM (Dynamic RAM) - high capacity, refresh needed SRAM (Static RAM) - low power, fast, easy to interface Timing CPU Memory System bus (data, address & control signals) Parallel I/O Serial I/O Interrupt circuitry Many wires, fast. Simple (only two wires + ground) but slow. At external unexpected events, P has to interrupt the main program execution, service the interrupt request (obviously a short subroutine) and retake the main program from the point where it was interrupt. Printer (high resolution) External memory Floppy Disk Hard Disk Compact Disk Other high speed devices Printer (low resolution) Modem Operator’s console Mainframe Personal computer

Processor (8086 / 8088 trough Pentium) The Personal Computer Speaker Processor (8086 / 8088 trough Pentium) Coprocessor (8087 trough 80387) Timer logic (8253) System ROM 640KB DRAM System bus (data, address & control signals) Keyboard logic (8253) DMA Controller (8237) Expansion logic Interrupt logic (8259) Video card Disk controller Serial port Keyboard ... Extension slots

Parts of the Central Processing Unit CPU performs the fetch/decode/execute cycle Fetch: Control Unit fetches next instruction Decode: Control Unit decodes instruction Execute: instruction is executed by appropriate component ALU Control Unit Parts of the Central Processing Unit Instruction (Input) ALU – Arithmetic and Logic Unit performs mathematical operations Control Unit coordinates all of the computer’s operations Result (Output) CPU

High-level languages: designed to be easy for humans to read and to write programs in, but too complicated for the computer to understand Z = X + Y Low-level languages: consist of simple instructions which can be understood by the computer after a minor translation ADD X Y Z Machine Language: written in the form of zeros and ones, can be understood directly by the computer 0110 1001 1010 1011

Evolution of Microprocessors Computers “generations” First generation ENIAC (vacuum tubes) Second generation (transistors) Third generation (IC - SSI, MSI) Fourth generation (LSI) Fifth generation can think? Microprocessors MSI Intel® 4004™, 8008™ LSI Intel® 8080™, Zilog® Z80™, Motorola® 6800™ 8 bit data bus, 16 bit address bus (64kbyte=65536 byte of addressable memory), no multiply and divide instructions VLSI 32…64 bit data bus, 2-300MHz clock, RISC concept

Hardware Terms & Functionality CPU: Performs all arithmetic & logical operations Memory: Used to store programs & data. Is divided into individual components called addresses Input/Output (I/O) devices: allow communication with the “real” world Mass storage: means of permanently storing programs and/or data System bus: Means by which other components communicate. Busses are grouped into three categories: Data lines: for transmitting data Address lines: indicate where information is sent to/from Control lines: regulate activity on the bus

In more detail, the architecture may look like the following: Memory Module Timing Memory Module CPU Bus Control I/O Module Mass Storage I/O Module Keyboard

Data Communication Control Interfaces frequently implemented in a microcomputer system. Dynamic RAM Bus Support ROM Static RAM Memory Control To Processor Data Communication Control Mass Storage Control Display Control Keyboard Control Hard Copy Control Other Device To Mass Storage Display Keyboard Printer

The 8086: the first 80x86 Machine

Evolution of the Intel Processors 8080 8051 80186 80386ex 8086/88 80286 80386 80486 Pentium Embedded Microprocessors/Microcontrollers General Purpose Microprocessors Pentium II 8086/88 80286 80386 80486 Pentium Code and System Level Compatability

The 8086: the first 80x86 Machine 8088 and 8086 pin assignments GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK Vcc A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 (HIGH) ___ MN/MX RD HOLD (RQ/GT0) ___ ____ HLDA (RQ/GT1) ___ ______ WR (LOCK) IO/M (S2) __ __ DT/R (SI) DEN (S0) ____ __ ALE (QS0) INTA (QS1) _____ TEST READY RESET 1 40 8088 20 21 GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK Vcc AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 ____ MN/MX ___ RD HOLD (RQ/GT0) ___ ____ HLDA (RQ/GT1) ___ ______ WR (LOCK) IO/M (S2) __ __ DT/R (SI) DEN (S0) ____ __ ALE (QS0) INTA (QS1) _____ TEST READY RESET 1 40 8086 20 21

Typical Microprocessor Memory System Control Memory CPU Address Data

8086 / 8088 Memory Interface Address Bus Data Bus Control Bus 20 address lines so a 220 byte address space Pins A0-A19 provide the address For 8086, A0-A15 appear multiplexed with D0-D15 to form AD0-AD15 For 8088, A0-A7 appear multiplexed with D0-D7 to form AD0-AD7 Data Bus For 8086, 16 bit data bus D0-D15 (multiplexed as AD0-AD15) For 8088, 8 bit data bus D0-D7 (multiplexed as AD0-AD7) 8086 may use only D0-D7 or D8-D15 if appropriate Control Bus For memory access, the following pins are used: RD’, WR’, M/IO’, DT/R’, DEN’, ALE, BHE’

General Architecture of the 8088/8086 Processors Segment Registers Instruction Pointer Address Generation and Bus Control Instruction Queue BUS General Registers Operands ALU Flags

Real mode and Protected mode operation Addressable memory: 8086 20 address lines => 1MB (Mega Byte) Pentium 32 address lines => 4096MB For compatibility, all the 80x86 family members start running in “Real Mode”, emulating the 8086 features (i.e. 1MB RAM) Beginning with 80286, the “Protected Mode” is also available, allowing direct control of all address lines (all addressable memory), multitasking support, virtual memory addressing, memory management and protection (against violation from other task), control over internal data and instruction cache.

Addresses Memory locations are comprised of groups of bits. 8 bits: 1 byte 16 bits: 1 word 32 bits: 1 double word 64 bits: 1 quad word Each byte has an associated address. Addresses are comprised of groups of bits. The set of all possible address bit combinations is called the ADDRESS SPACE.

The Software Model of 80x86 Family 15 . . . 8,7 . . . 0 15 . . . 8,7 . . . 0 31 . . . . . . 16,15 . . . 8,7 . . . 0 Accumulator Base Count Data Base Pointer Source Index Destination Index Code Segment Data Segment Stack Segment Extra Segment FS GS Extended registers, only on 80386 and higher CPUs Instruction Pointer Stack Pointer Flags 32 bit registers, 80386 or higher only 8 bit registers 16 bit registers

Processor Registers A000 + 5F00 A5F00 15 . . . 8,7 . . . 0 A prefix (66H) allows using 32 bit registers in the real mode: db 66h ;EAX instead AX mov ax,1140h ;less significant 16 bits db 058bh ;most significant 16 bits Accumulator Base Count Data Base Pointer Source Index Destination Index Multiply, divide, accessing I/O... Counter in loop operations Multiply, divide, pointer to I/O... Source index in string operations... Destination index in string operations Segment = a 64kbyte memory block beginning at a multiple by 10H address. Code Segment Data Segment Stack Segment Extra Segment Shift to left 4 bits An effective address is generated as combination between a segment register and another register as in the example. 16 bit FS GS A000 + 5F00 A5F00 Add Each segment register has a default usage (class of instructions where apply). 16 bit Instruction Pointer Stack Pointer Flags Pointer in program flow Pointer in Stack Control and status flags Effective Address (20bits) 16 bit registers

Flag register CF PF AF ZF SF TF IF DF OF IOPL NT Carry Flag Parity Flag Auxiliary carry Flag Zero Flag Sign Flag Trace Flag Interrupt enable Flag Direction Flag Overflow Flag I/O Priority Level Nested Task Contains Carry out of MSB of result Indicates if result has even parity Contains Carry out of bit 3 in AL Indicates if result equals zero Indicates if result is negative Provides a single step capability for debugging Enables/disables interrupts Controls pointer updating during string operations Indicates that an overflow occurred in result Priority level of current task (two bits) Indicates if current task is nested

Data Organization Bits, Bytes, Words, Double-words Possible Values Binary Hexadecimal Decimal 0,1 0,1 0,1 0...1111 0...F 0…15 0…1111,1111 0…FF 0…255 0…(16 ‘1’s) 0…FFFF 0…65,535 0…(32 ‘1’s) 0…FFFFFFFF 0...4,294,967,295 Name Bit Nibble Byte Word Double Word Size BInary digiT 4 bits 8 bits 16 bits = 2 bytes 32 bits = 4 bytes Byte swapping: if a word has to be stored into an 8 bit wide memory at address adr, its low byte is stored at adr and its high byte at adr+1. If a word is read from an 8 bit memory at address adr, the low byte is loaded from adr and the high byte from adr+1. Rule: low significance <=> low address

Instruction types Data transfer instructions 8086 instruction set IN Input byte or word from port LAHF Load AH from flags LDS Load pointer using data segment LEA Load effective address LES Load pointer using extra segment MOV Move to/from register/memory OUT Output byte or word to port POP Pop word off stack POPF Pop flags off stack PUSH Push word onto stack PUSHF Push flags onto stack SAHF Store AH into flags XCHG Exchange byte or word XLAT Translate byte Additional 80386 instructions LFS Load pointer using FS LGS Load pointer using GS LSS Load pointer using SS MOVSX Move with sign extended MOVZX Move with zero extended POPAD Pop all double (32 bit) registers POPD Pop double register POPFD Pop double flag register PUSHAD Push all double registers PUSHD Push double register PUSHFD Push double flag register Additional 80486 instruction BSWAP Byte swap Additional 80286 instructions INS Input string from port OUTS Output string to port POPA Pop all registers PUSHA Push all registers Additional Pentium instruction MOV Move to/from control register

Instruction types Arithmetic instructions 8086 instruction set AAA ASCII adjust for addition AAD ASCII adjust for division AAM ASCII adjust for multiply AAS ASCII adjust for subtraction ADC Add byte or word plus carry ADD Add byte or word CBW Convert byte or word CMP Compare byte or word CWD Convert word to double-word DAA Decimal adjust for addition DAS Decimal adjust for subtraction DEC Decrement byte or word by one DIV Divide byte or word IDIV Integer divide byte or word IMUL Integer multiply byte or word INC Increment byte or word by one MUL Multiply byte or word (unsigned) NEG Negate byte or word SBB Subtract byte or word and carry (borrow) SUB Subtract byte or word Additional 80386 instructions CDQ Convert double-word to quad-word CWDE Convert word to double-word Additional 80486 instructions CMPXCHG Compare and exchange XADD Exchange and add Additional Pentium instruction CMPXCHG8B Compare and exchange 8 bytes

Instruction types Bit manipulation instructions 8086 instruction set AND Logical AND of byte or word NOT Logical NOT of byte or word OR Logical OR of byte or word RCL Rotate left trough carry byte or word RCR Rotate right trough carry byte or word ROL Rotate left byte or word ROR Rotate right byte or word SAL Arithmetic shift left byte or word SAR Arithmetic shift right byte or word SHL Logical shift left byte or word SHR Logical shift right byte or word TEST Test byte or word XOR Logical exclusive-OR of byte or word Additional 80386 instructions BSF Bit scan forward BSR Bit scan reverse BT Bit test BTC Bit test and complement BTR Bit test and reset BTS Bit test and set SETcc Set byte on condition SHLD Shift left double precision SHRD Shift right double precision

Instruction types String instructions 8086 instruction set CMPS Compare byte or word string LODS Load byte or word string MOVS Move byte or word string MOVSB(MOVSW) Move byte string (word string) REP Repeat REPE (REPZ) Repeat while equal (zero) REPNE (REPNZ) Repeat while not equal (not zero) SCAS Scan byte or word string STOS Store byte or word string