Lecture 2: Basic Instructions CS 2011 Fall 2014, Dr. Rozier

PROBLEM SETS

Consider the following processors, P1, P2, and P3 executing the same instruction set with clock rates and CPI as indicated 1.Which processor has the highest performance in terms of instructions per second? 2.If the processors each execute a program in 10s, find the number of cycles and the number of instructions 3.We are trying to reduce the execution time by 30% but this leads to an increase in CPI of 20%. What clock rate should we have to get this reduction? ProcessorClock RateCPI P13 GHz1.5 P22.5 GHz1.0 P34 GHz2.2

Consider a computer running code with four main routines, A, B, C, and D. 1.How much is the total time reduced if the time for Routine A is reduced by 20%? 2.How much is the time for Routine B reduced if the total time is reduced by 20%? 3.Can the total time be reduced by 20% by only reducing the time for Routine D? Routine ARoutine BRoutine CRoutine DTotal Time 40s90s60s20s210s

Consider a computer running code with four main routines, A, B, C, and D. 1.How much is the total time reduced if the time for Routine A is reduced by 20%? 2.How much is the time for Routine B reduced if the total time is reduced by 20%? 3.Can the total time be reduced by 20% by only reducing the time for Routine D? Routine ARoutine BRoutine CRoutine DTotal Time Exec Time40s90s60s20s210s Instructions50x10^6110x10^680x10^616x10^6- Avg CPI1142-

Consider a computer running code with four main routines, A, B, C, and D. 1.How much must we improve the CPI of Routine A if we want the program to run twice as fast? 2.How much must we improve the CPI of Routine C if we want the program to run twice as fast? 3.How much is the execution time improved if the CPI of routines A and B are reduced by 40%, and the CPI of routines C and D are reduced by 30%? Routine ARoutine BRoutine CRoutine DTotal Time Exec Time40s90s60s20s210s Instructions50x10^6110x10^680x10^616x10^6- Avg CPI1142-

REPRESENTING NUMBERS

Networking and Communication What if we encode the signal into pulses? Detect if the value is above or below some threshold, and decide it represents a 1, or a 0. Strings of 1’s and 0’s can be interpreted as a number.

Some simple things we can represent with 1’s and 0’s True or false… – 1 – true – 0 – false – We already were doing this with pure signals.

Some simple things we can represent with 1’s and 0’s Integers Examples – – – – – 10 – – – 147

Unsigned Binary Integers Given an n-bit number Range: 0 to +2 n – 1 Example = 0 + … + 1× ×2 2 +1×2 1 +1×2 0 = 0 + … = Using 32 bits 0 to +4,294,967,295

Hexadecimal Base 16 – Compact representation of bit strings – 4 bits per hex digit c d a1010e b1011f1111 Example: eca

BASIC INSTRUCTIONS

Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets – But with many aspects in common Early computers had very simple instruction sets – Simplified implementation Many modern computers also have simple instruction sets

MIPS vs ARMv6 The book uses the MIPS instruction set. We will be using ARMv6 in our labs. Both are RISC (reduced instruction set computer) architectures. – Many similarities.

MIPS Used in many embedded systems – Routers, gateways – Playstation 2 and PSP Invented by Prof John Hennessy at Stanford, the first RISC architecture.

ARM Introduced in 1985 Focused on low-power friendly operation. Since 2005, over 98% of all mobile phones had at least one ARM processor. Over 37 billion ARM processors in use in Rapidly becoming the dominant processor architecture in the world.

Instructions C code: – f = (g + h) – (i + j); Compile ARM code: – add r0, r3, r4 # temp t0 = g + h – add r1, r5, r6 # temp t1 = i + j – sub r2, r0, r1 # f = t0 – t1

Register Operands Instructions use registers for operands. Registers are extremely fast SRAM locations that are directly accessible by the processor. – Very fast, but very expensive, so very small.

Registers Each register holds a word (4 bytes). Registers r0-r12 are general purpose. NameFunctionNameFunction r0General Purposer8General Purpose r1General Purposer9General Purpose r2General Purposer10General Purpose r3General Purposer11General Purpose r4General Purposer12General Purpose r5General Purposer13Stack Pointer r6General Purposer14Link Register r7General Purposer15Program Counter

Registers Registers r13 – r15 have special purposes The PC, r15, is very dangerous. NameFunctionNameFunction r0General Purposer8General Purpose r1General Purposer9General Purpose r2General Purposer10General Purpose r3General Purposer11General Purpose r4General Purposer12General Purpose r5General Purposer13Stack Pointer r6General Purposer14Link Register r7General Purposer15Program Counter

Registers The register r13 holds the stack pointer – Also called sp – Points to a special part of memory called the stack. – More about this later.

Registers The register r14 holds the link register – Also called lr – Holds the value of a return address that allows for fast and efficient implementation of subroutines.

Registers The register r15 holds the program counter – Also called pc – Holds an address of an instruction. Keeps track of where your program is in its execution of machine code. – PC holds the address of the instruction to be fetched next.

Registers One additional register, the “current program status register” Four most significant bits hold flags which indicate the presence or absence of certain conditions …87654…0 NZCVReservedIFTMODE

Registers N – negative flag Z – zero flag C – carry flag V – overflow flag …87654…0 NZCVReservedIFTMODE

Registers N – set by an instruction if the result is negative (set equal to the two’s complement sign bit) N – negative flag Z – zero flag C – carry flag V – overflow flag …87654…0 NZCVReservedIFTMODE

Registers Z – set by an instruction if the result of the instruction is zero. N – negative flag Z – zero flag C – carry flag V – overflow flag …87654…0 NZCVReservedIFTMODE

Registers C – set by an instruction if the result of an unsigned operation overflows the 32-bit register. Can be used for 64-bit arithmetic N – negative flag Z – zero flag C – carry flag V – overflow flag …87654…0 NZCVReservedIFTMODE

Registers V – works the same as the C flag, but for signed operations. N – negative flag Z – zero flag C – carry flag V – overflow flag …87654…0 NZCVReservedIFTMODE

MORE ABOUT THESE LATER…

The Memory Hierarchy

Load-Store Architecture RISC architectures, like ARM and MIPS utilize a load-store architecture. Memory cannot be part of arithmetic operations. – Only registers can do this Access memory is through loads and stores.

Register Memory Architecture Featured on many CISC architectures, like x86 Allows direct access to memory by instructions.

Load Store and ARM Register space is pretty cramped!!! LoaD to a Register with LDR SToRe to memory with STR ldr, [ {, }] – Loads a byte from + into str, [ {, }] – Stores a byte from into +

Load Store and ARM Example – ldr r0, [r1,r2] Load data from location r1+r2 into r0. – ldr r0, =string Load data from label string into r0. Special cases exist, see ARM manual – Example: ldrb loads a single byte, padded with zeros.

Constants or Immediates Operands can contain registers, or immediate values. – An immediate is like a constant – Represent immediates as follows: #20 add r0, r1, #20 – adds 20 to the value of r1 and stores it in r0.

Arithmetic Instructions Addition – add, adc, adds, etc Subtraction – sub, sbc, rsb, subs, etc Multiply – mul, mla, etc

Move Instruction mov, – mov r0, r1 – copy the contents of r1 into r0. – mov r0, #20 – copy an immediate value of 20 into r0. mvn, – Move negative, negates operand before copying it.

Compare Instructions cmp, cmn, Don’t change the operands, update special status register flags. cmp – subtracts operand2 from operand1 and discards the result. cmn – adds operand2 to operand1 and discards the result.

Status Register Flags Compare instructions and the special “S” versions of instructions (adds, subs, movs) set the status register flags. Can be used with conditional suffixes to make conditionally executed instructions.

Conditional Execution Just as the special “S” suffix can be added to set status flags, other suffixes can be added to act on status flags.

EQ: Equal Z=1 Using the EQ suffix on an instruction will cause it to only be executed if the zero flag is set. cmp r0, Set flags based on r0-r1 adds r0, r1, Set flags based on r0 = r1 + r2 movs r0, Set flags based on r0 = r1

EQ: Equal Z=1 Using the EQ suffix on an instruction will cause it to only be executed if the zero flag is set. Example cmp r0, Set flags based on r0-r1 addeq r2, r0, Conditional addition

NE: Equal Z=0 Using the NE suffix on an instruction will cause it to only be executed if the zero flag is not set.

Other conditional suffixes VS – overflow set, V=1 VC – overflow clear, V=0 MI – minus set, N=1 PL – minus clear, N=0 CS – carry set, C=1 CC – carry clear, C=0 AL – always, unconditional NV – never, unconditional

Multiple Conditional Suffixes HI – higher (unsigned), C=1 and Z=0 – Unsigned greater than LS – lower (unsigned), C=0 and Z=1 – Unsigned less than GE – greater or equal (signed), N=1, V=1 OR N=0, V=0 – Signed greater than or equal to LT – less than (signed), N=1, V=0, OR N=0,V=1 – Signed less than

Multiple Conditional Suffixes GT – greater than (signed), N=1, V=1, OR N=0, V=0 AND Z=0 – Signed greater than LE – less than or equal (signed), N=1, V=0, OR N=0, V=1, OR Z=1 – Signed less than or equal to

For next time Continue discussion on basic instructions.