2. Super KEKB Meeting, DEPFET Electronics DEPFET Readout and Control Electronics Ivan Peric, Peter Fischer, Christian Kreidl Heidelberg University

2. Super KEKB Meeting, DEPFET Electronics Outline -Module Electronics - Introduction -Principle of DEPFET readout -Switcher with LV transistors (Switcher 3) -Switcher with HV transistors -DCD Chip -Bumping technologies

2. Super KEKB Meeting, DEPFET Electronics DEPFET readout and control-ASICS

2. Super KEKB Meeting, DEPFET Electronics DEPFET readout and control-ASICS DCD#0 – DCD#5 Switcher#0 Switcher#4 ACTIVE AREA Sensor – active area Sensor balcony Chip Switcher – row control chip with high voltage line drivers 0.35 μm technology DCD – DEPFET current receiver and digitizer chip 0.18 μm technology DHP – Digital data handling and readout control chip 0.09 μm technology 960X512 (160 channels each) (32 channels each) Bump bonding Fan-out Switcher DCD DHP

2. Super KEKB Meeting, DEPFET Electronics Layout (Preliminary) DCDs Switcher Width = 1.6mm!

2. Super KEKB Meeting, DEPFET Electronics Principle of DEPFET readout

2. Super KEKB Meeting, DEPFET Electronics Readout principle 1 – signal collection – internal gate p+ Internal gate (n+) PMOS n+ DEPFET pixel n-(depleted) G DSClr DHP DCD#0 – DCD#5 SWITCHER#0 SWITCHER#4 ACTIVE AREA Signal generation Signal collection

2. Super KEKB Meeting, DEPFET Electronics Readout principle – start of the readout p+ Internal gate (n+) PMOS n+ DEPFET pixel n-(depleted) G DSClr DHP DCD#0 – DCD#5 SWITCHER#0 SWITCHER#4 ACTIVE AREA Signal collection Signal generation Read out

2. Super KEKB Meeting, DEPFET Electronics G DHP DCD#0 – DCD#5 SWITCHER#0 SWITCHER#4 ACTIVE AREA Readout principle – switcher generates high voltage – row on p+ Internal gate (n+) PMOS n+ DEPFET pixel n-(depleted) DSClr Signal collection Signal generation Read out Row on

2. Super KEKB Meeting, DEPFET Electronics Readout principle – drain current is stored in DCD DHP DCD#0 – DCD#5 SWITCHER#0 SWITCHER#4 ACTIVE AREA p+ Internal gate (n+) PMOS n+ DEPFET pixel n-(depleted) DSClr Signal collection Signal generation Read out Row on Signal memorizing

2. Super KEKB Meeting, DEPFET Electronics Readout principle – start of clearing DHP DCD#0 – DCD#5 SWITCHER#0 SWITCHER#4 ACTIVE AREA p+ Internal gate (n+) PMOS n+ DEPFET pixel n-(depleted) DSClr Signal collection Signal generation Read out Row on Signal memorizing Clearing

2. Super KEKB Meeting, DEPFET Electronics Readout principle – clearing, offset current subtracted in DCD DHP DCD#0 – DCD#5 SWITCHER#0 SWITCHER#4 ACTIVE AREA p+ Internal gate (n+) PMOS n+ DEPFET pixel n-(depleted) DSClr Signal collection Signal generation Read out Row on Signal memorizing Clearing Signal – offest subtraction

2. Super KEKB Meeting, DEPFET Electronics Readout principle – A/D conversion p+ Internal gate (n+) PMOS n+ DEPFET pixel n-(depleted) G DSClr DHP DCD#0 – DCD#5 SWITCHER#0 SWITCHER#4 ACTIVE AREA Signal collection Signal generation Read out Row on Signal memorizing Clearing Signal – offest subtraction A/D conversion

2. Super KEKB Meeting, DEPFET Electronics Row control “Switcher” chip

2. Super KEKB Meeting, DEPFET Electronics Switcher with LV transistors – Switcher 3 Switcher 3 Radiation tolerant layout in 0.35 μm technology 128 channels + Very fast - Operation up to 11.5 V Novel design: Uses stacked LV transistors, HV twin-wells and capacitors as level- shifters + No DC power consumption HV channel with 3+3 Switch transistors and 4 AC coupling stages (180x180µm, M4 not shown) interdigitated AC coupling caps Ivan Peric, Mannheim 80µm opening

2. Super KEKB Meeting, DEPFET Electronics Switcher 3 – output driver Use an SRAM cell flipped by a transient voltage No dc power consumption! 9V out ‘SRAM’ 3V ‘SRAM’ 6V ‘SRAM’ 0V 3V 6V Reset ~200 fF

2. Super KEKB Meeting, DEPFET Electronics Switcher with LV transistors – Switcher 3

2. Super KEKB Meeting, DEPFET Electronics Rising/Falling Edge vs. C load 2ns ! 9V ! 0pF (1.8ns) 10pF (4ns) 22pF (8ns) 47pF (18ns) 0pF (1.5ns) 10pF (3.8ns) 22pF (6.5ns) 47pF (14ns)

2. Super KEKB Meeting, DEPFET Electronics Switcher 3 chip irradiation up to 22 MRad Only degradation in speed which can be avoided using larger transistors

2. Super KEKB Meeting, DEPFET Electronics Switcher 4 Switcher 3 Uses radiation tolerant high voltage transistors in HV 0.35 μm technology 64 channels + fast enough + Possible operation up to 50 V (30V tested) + low DC power consumption Enclosed design of NMOS HV transistors

2. Super KEKB Meeting, DEPFET Electronics Switcher 4 chip – high voltage transistors Hi voltage 20V0V 17-20V0-3V 0-20V Thin oxide Thick oxide n- p- n- Vertical NMOS PMOS

2. Super KEKB Meeting, DEPFET Electronics D S D S Thick oxidLeakage current Standard NMOS Annular gate NMOS G G Annular gate vertical NMOS S B G D Difefrent types of radiation-soft and -hard NMOS transistors

2. Super KEKB Meeting, DEPFET Electronics logic out 20V 17V 3V 0V in Switcher 4 chip output driver

2. Super KEKB Meeting, DEPFET Electronics logic out 20V 17V 3V 0V in Switcher 4 chip output driver 30V amplitude

2. Super KEKB Meeting, DEPFET Electronics Irradiation of NMOS transistors X-ray irradiation up to ~600 krad No threshold shift or leakage current for annular structures 600 krad before stacked ‘normal’ annular NMOS ‘HV’ NMOS: thin gate oxide, extended thick drain, enclosed gate ‘HV’ NMOS, normal layout

2. Super KEKB Meeting, DEPFET Electronics DEPFET signal digitizer chip - DCD

2. Super KEKB Meeting, DEPFET Electronics DCD3 chip - Technology 0.18 μm - 72 Channels - 2 ADCs and regulated cascode/channel - 6 channels multiplexed to one digital LVDS output - ADC sampling period 160 ns (8 bits) - Channel sampling period 80 ns - LVDS output: 600 M bits/s - Chip: 7.2 G bits/s (12 outputs) - Radiation tolerant design - ~ 1mW/ADC

2. Super KEKB Meeting, DEPFET Electronics DCD3 chip

2. Super KEKB Meeting, DEPFET Electronics DCD3 ADC Reg. cascode Double sampling DEPFET W NC R R R R L L R R W R R L L W R Gate On

2. Super KEKB Meeting, DEPFET Electronics DCD 3 measurements ADC characteristicNoise

2. Super KEKB Meeting, DEPFET Electronics DCD 3 irradiation up to 7 MRad No significant changes after 7 Mrad and 6 days of annealing ADC characteristicAnalog characteristic of CSC Noise – channel 1Noise – channel 2

2. Super KEKB Meeting, DEPFET Electronics Chip Geometry: 1525 µm x 5000 µm Technology 0.18 μm Analog circuits in upper pixels Digital circuits on the bottom 10 x 16 ANALOG parts (bump + cascode + current memory + ADC) Analog Power pads Digital Power Pads Digital Outputs Control DIGITAL 10 x 4 outputs + control Pitch = 150µm Chip architecture – (proposed for SBelle prototype)

2. Super KEKB Meeting, DEPFET Electronics Channel layout – (proposed for SBelle prototype) AAA AAA Bump-bond pad (Analog In) Cell1Cell2 A A h, l CmpHiCmpLoCell3Cell4CmpHiCmpLo A TC MM cap TC (Receiver) Digital output ADC1 ADC2 Sampling cell 1 Sampling cell 2 Reg. cascode IO line

2. Super KEKB Meeting, DEPFET Electronics Data handling processor - DHP

2. Super KEKB Meeting, DEPFET Electronics DHP architecture

2. Super KEKB Meeting, DEPFET Electronics DHP - block diagram of the data processing block

2. Super KEKB Meeting, DEPFET Electronics Bumping

2. Super KEKB Meeting, DEPFET Electronics Base technology – chip with gold stuts

2. Super KEKB Meeting, DEPFET Electronics 1. Gold Studs 2. Buy chips with PbSn bumps or similar (possible for UMC via SPIL wafer bumping service, IBM,…) 3. Get everything done by company TechnoMin. pitch Bump pad Max. bumps Pressure / bump UBM Sensor Wafers Needed ReworkCostWho Au Stud10070 (60)600>25gno NoLow HD, (BN, HLL) Bumped Chips (?)  0yesNoYesMed HD, (BN, HLL) Deposit PbSn ~10070(?)  0yesNoYesLow PACTEC (HD ?) By vendor 5015  0yes YesHighIZM,… Bumping possibilities

2. Super KEKB Meeting, DEPFET Electronics Conclusions - DCD prototype chip has been tested with test signals that correspond to DEPFET currents and irradiated up to 7 Mrad. The chip works fine and has high enough conversion speed. Operation with matrices still to be tested – we do not expect problems. Only „fine tuning“ of the design for the super KEKB operation is necessary. - Switcher prototype with LV transistors has been tested and irradiated up to 22 MRad. The chip works fine and has adequate speed for SBelle operation. - Another prototype with HV transistors has been designed and tested. - The irradiation of the chip still has to be done but the basic and most critical part (high-voltage NMOS) has been irradiated up to 600 KRad and no damage has been observed. - DHP chip will be designed using digital design tools in intrinsically radiation hard 90 nm technology. - Choice between 4 different bumping technologies – advantages and disadvantages still to be evaluated…

2. Super KEKB Meeting, DEPFET Electronics Thank you

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 2) Reg. cascode Double sampling DEPFET W NC R R R R L L R R W R R L L W R Gate On

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 3) Reg. cascode Double sampling DEPFET NC W R R C C L L W R R C C L L W R Z

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 4) Reg. cascode Double sampling DEPFET R R W NC L L R R R W R L L R R W R C

2. Super KEKB Meeting, DEPFET Electronics Clear On DCD2 (CNT = 5) 77 Reg. cascode Double sampling DEPFET R R NC W L L C C R W R L L C C R W Z

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 6) Reg. cascode Double sampling DEPFET W NC R R R R L L R R W R R L L R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 7) Double sampling NC W R R C C L L W R R C C L L Reg. cascode DEPFET R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 8) Double sampling R R W NC L L R R R W R L L R R Reg. cascode DEPFET R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 9) Double sampling R R NC W L L C C R W R L L C C Reg. cascode DEPFET R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 10) Reg. cascode Double sampling DEPFET W NC R R R R L L R R W R R L L W R Gate On

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 11) Reg. cascode Double sampling DEPFET NC W R R C C L L W R R C C L L W R Z

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 12) Reg. cascode Double sampling DEPFET R R W NC L L R R R W R L L R R W R C

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 13) Reg. cascode Double sampling DEPFET R R NC W L L C C R W R L L C C R W Z Clear On

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 14) Reg. cascode Double sampling DEPFET W NC R R R R L L R R W R R L L R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 15) Double sampling NC W R R C C L L W R R C C L L Reg. cascode DEPFET R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 0) Double sampling R R W NC L L R R R W R L L R R Reg. cascode DEPFET R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 1) Double sampling R R NC W L L C C R W R L L C C Reg. cascode DEPFET R W

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 2) Reg. cascode Double sampling DEPFET W NC R R R R L L R R W R R L L W R Gate On

2. Super KEKB Meeting, DEPFET Electronics DCD2 (CNT = 3) Reg. cascode Double sampling DEPFET NC W R R C C L L W R R C C L L W R Z