MICAS Department of Electrical Engineering (ESAT) Update of the “Digital EMC project” January 19th, 2006 AID–EMC: Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS

MICAS Department of Electrical Engineering (ESAT) Outline 1. Circuit structure 2. Maple simulation 3. Spectre simulation 4. Future work

MICAS Department of Electrical Engineering (ESAT) Coupling problem ! Cgs 1,2 ≈ Cgd1 ∆ V DD_input ∆ V bias

MICAS Department of Electrical Engineering (ESAT) Why new structure ? 1.Simple 2.Driving capability 3.Miller effect on compensation capacitor 4.Cascode device: decrease coupling from VDD_input to VDD provided that Vbias is biased as a low impedance node

MICAS Department of Electrical Engineering (ESAT) Stability analysis Stability as a function of I load (26.7u A ~ 72m A) Raux=1.852K, Caux=20p φ ≥ 60 ° Worst case

MICAS Department of Electrical Engineering (ESAT) Maple calculation An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation

MICAS Department of Electrical Engineering (ESAT) Comparison with old structure New structure Old structure ~10 reduction !!

MICAS Department of Electrical Engineering (ESAT) Spectre simulation – TF H(s)=Idd(s)/Iout(s) Future: Theoretical Expression of TF TF as a function of Caux

MICAS Department of Electrical Engineering (ESAT) Relation with Gabarit ? ? emission limit example: H-12-n-O Source: from Herman Casier

MICAS Department of Electrical Engineering (ESAT) Emergency block and PD block

MICAS Department of Electrical Engineering (ESAT) Shift register cell Determine the current peak and duration: FF Din CLK RST Out 600 [uA] × 50 × 12= 360 [mA] Then, the output current of the special regulator : 36 [mA] ~ 72 [mA] 50 FF gates 10 ×5×5× Source: from Aarnout Wieers

MICAS Department of Electrical Engineering (ESAT) Top level simulation Current source simulation Frequency simulation

MICAS Department of Electrical Engineering (ESAT) Current source simulation of whole circuit Current of Vbat VDD after the regulator VDD_input Power down enable

MICAS Department of Electrical Engineering (ESAT) Current source simulation of whole circuit Current of Vbat V3v3 VDD_input Vcontrol Power down enable

MICAS Department of Electrical Engineering (ESAT) Frequency simulation of the whole circuit current of Vbat di/dt p-p =8.5x10 4 [A/s] 9x10 6 load current FFT di/dt p-p =1.8x10 9 [A/s] 7x10 3

MICAS Department of Electrical Engineering (ESAT) Layout Area: 1mm x 1.1mm Ctank Caux Ctank Ctank and Power transistors

MICAS Department of Electrical Engineering (ESAT) EMC test chip with special regulator SR1, MS-FF, PMOS capa SR2, MS-FF, NMOS capa SR3, MS-FF, MIM capa SR4, D-FF, PMOS capa SR5, D-FF, NMOS capa SR6, D-FF, MIM capa SR7, MS-FF, no capa, PWR on GND SR8, MS-FF, no capa, PWN next GND SR9, MS-FF, no capa, PWR next GND SR10, D-FF, no capa, PWR on GND SR11, D-FF, no capa, PWR next GND SR12, D-FF, no capa, PWR next GND On-chip LDR PD On-chip Serial regulator PD SR1 RST Din CLK OUT SR2 RST Din CLK OUT SR11 RST Din CLK OUT SR12 RST Din CLK OUT GND Kelvin contact LDO PD Special (KUL) regulator Ctank Source: from Aarnout Wieers

MICAS Department of Electrical Engineering (ESAT) Future work 1. Chip measurement Design improvement Refine Theoretical analysis on EMC reduction and maximum current capability 2. Continue research on the Clock strategy: SSCG

MICAS Department of Electrical Engineering (ESAT) Questions Thank you for your attention