8-1 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 8: Input and Output

8-2 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Chapter Contents 8.1 Simple Bus Architectures 8.2 Bridge-Based Bus Architectures 8.3 Communication Methodologies 8.4 Case Study: Communication on the Intel Pentium Architecture 8.5 Mass Storage 8.6 Input Devices 8.7 Output Devices

8-3 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Simple Bus Architecture A simplified motherboard of a personal computer (top view):

8-4 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Simplified Illustration of a Bus

8-5 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization 100 MHz Bus Clock

8-6 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization The Synchronous Bus Timing diagram for a synchronous memory read (adapted from [Tanenbaum, 1999]).

8-7 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization The Asynchronous Bus Timing diagram for asynchronous memory read (adapted from [Tanenbaum, 1999]).

8-8 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Bus Arbitration (a)Simple centralized bus arbitration; (b) centralized arbitration with priority levels; (c) decentralized bus arbitration. (Adapted from [Tanenbaum, 1999]).

8-9 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Bridge Based Bus Arch- itecture Bridging with dual Pentium II Xeon processors on Slot 2. (Source: com.)

8-10 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Programmed I/O Flowchart for a Disk Transfer

8-11 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Interrupt Driven I/O Flowchart for a Disk Transfer

8-12 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization DMA Transfer from Disk to Memory Bypasses the CPU

8-13 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization DMA Flowchart for a Disk Transfer

8-14 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Intel Memory and I/O Address Spaces

8-15 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Standard Intel Pentium Read and Write Bus Cycles

8-16 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Intel Pentium Burst Read Bus Cycle

8-17 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Intel Pentium Hold-Hold Acknow- ledge Bus Cycle

8-18 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization A Magnetic Disk with Three Platters

8-19 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Manchester Encoding (a) Straight amplitude (NRZ) encoding of ASCII ‘F’; (b) Manchester encoding of ASCII ‘F’.

8-20 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Organization of a Disk Platter with a 1:2 Interleave Factor

8-21 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Master Control Block

8-22 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Magnetic Tape A portion of a magnetic tape (adapted from [Hamacher, 1990]).

8-23 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Magnetic Drum

8-24 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Spiral Format for Compact Disk

8-25 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization ECMA-23 Keyboard Layout Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys are frequently placed in the B row.

8-26 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization The Dvorak Keyboard Layout

8-27 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Bit Pad with Puck

8-28 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Mouse and Trackball A three-button mouse (left) and a three-button trackball (right).

8-29 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Lightpen A user selects an object with a lightpen.

8-30 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Touchscreen A user selects an object on a touchscreen.

8-31 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Joystick A joystick with a selection button and a rotatable rod:

8-32 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Laser Printer Schematic of a laser printer (adapted from [Tanenbaum, 1999]).

8-33 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Cathode Ray Tube A CRT with a single electron gun:

8-34 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization Display Controller Display controller for a 640  480 color monitor (adapted from [Hamacher et al., 1990]).

8-35 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization VHDL Specification Interface specification for the majority component -- Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT F_OUT: out BIT); end MAJORITY; Behavioral model for the majority component -- Body architecture LOGIC_SPEC of MAJORITY is begin -- compute the output using a Boolean expression F_OUT <= (not A_IN and B_IN and C_IN) or (A_IN and not B_IN and C_IN) or (A_IN and B_IN and not C_IN) or (A_IN and B_IN and C_IN) after 4 ns; end LOGIC_SPEC;

8-36 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization VHDL Specification (cont’) -- Package declaration, in library WORK package LOGIC_GATES is component AND3 port (A, B, C : in BIT; X : out BIT); end component; component OR4 port (A, B, C, D : in BIT; X : out BIT); end component; component NOT1 port (A : in BIT; X : out BIT); end component; -- Interface entity MAJORITY is port (A_IN, B_IN, C_IN: in BIT F_OUT: out BIT); end MAJORITY;

8-37 Chapter 8 - Input and Output Department of Information Technology, Radford University ITEC 352 Computer Organization VHDL Specification (cont’) -- Body -- Uses components declared in package LOGIC_GATES -- in the WORK library -- import all the components in WORK.LOGIC_GATES use WORK.LOGIC_GATES.all architecture LOGIC_SPEC of MAJORITY is -- declare signals used internally in MAJORITY signal A_BAR, B_BAR, C_BAR, I1, I2, I3, I4: BIT; begin -- connect the logic gates NOT_1 : NOT1 port map (A_IN, A_BAR); NOT_2 : NOT1 port map (B_IN, B_BAR); NOT_3 : NOT1 port map (C_IN, C_BAR); AND_1 : AND3 port map (A_BAR, B_IN, C_IN, I1); AND_2 : AND3 port map (A_IN, B_BAR, C_IN, I2); AND_3 : AND3 port map (A_IN, B_IN, C_BAR, I3); AND_4 : AND3 port map (A_IN, B_IN, C_IN, I4); OR_1 : OR3 port map (I1, I2, I3, I4, F_OUT); end LOGIC_SPEC;