Author : Jing Lin, Xiaola Lin, Liang Tang Publish Journal of parallel and Distributed Computing MAKING-A-STOP: A NEW BUFFERLESS ROUTING ALGORITHM FOR ON-CHIP.

Slides:

Advertisements

Similar presentations

Prof. Natalie Enright Jerger

Advertisements

A Novel 3D Layer-Multiplexed On-Chip Network

Presentation of Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip by Christian Neeb and Norbert Wehn and Workload Driven Synthesis.

Evaluating Bufferless Flow Control for On-Chip Networks George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis Stanford University.

1 Message passing architectures and routing CEG 4131 Computer Architecture III Miodrag Bolic Material for these slides is taken from the book: W. Dally,

PRESENTED BY: PRIYANK GUPTA 04/02/2012 Generic Low Latency NoC Router Architecture for FPGA Computing Systems & A Complete Network on Chip Emulation Framework.

Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks ______________________________ John Kim, William J. Dally &Dennis Abts Presented.

What is Flow Control ? Flow Control determines how a network resources, such as channel bandwidth, buffer capacity and control state are allocated to packet.

Allocator Implementations for Network-on-Chip Routers Daniel U. Becker and William J. Dally Concurrent VLSI Architecture Group Stanford University.

1 Lecture 17: On-Chip Networks Today: background wrap-up and innovations.

1 Lecture 12: Interconnection Networks Topics: dimension/arity, routing, deadlock, flow control.

Network based System on Chip Final Presentation Part B Performed by: Medvedev Alexey Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006.

CSE 291-a Interconnection Networks Lecture 12: Deadlock Avoidance (Cont’d) Router February 28, 2007 Prof. Chung-Kuan Cheng CSE Dept, UC San Diego Winter.

Traffic Forecasting Medium Access TRANSFORMA Vladislav Petkov Katia Obraczka 1.

1 Lecture 16: On-Chip Networks Today: on-chip networks background.

Network based System on Chip Part A Performed by: Medvedev Alexey Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006.

Lei Wang, Yuho Jin, Hyungjun Kim and Eun Jung Kim

1 Lecture 21: Router Design Papers: Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO’03, Princeton A Gracefully Degrading and.

1 Lecture 13: Interconnection Networks Topics: flow control, router pipelines, case studies.

1 Lecture 25: Interconnection Networks Topics: flow control, router microarchitecture Final exam:  Dec 4 th 9am – 10:40am  ~15-20% on pre-midterm  post-midterm:

Predictive Load Balancing Reconfigurable Computing Group.

1 Lecture 24: Interconnection Networks Topics: topologies, routing, deadlocks, flow control Final exam reminders:  Plan well – attempt every question.

1 Lecture 24: Interconnection Networks Topics: topologies, routing, deadlocks, flow control.

1 Lecture 26: Interconnection Networks Topics: flow control, router microarchitecture.

1 Indirect Adaptive Routing on Large Scale Interconnection Networks Nan Jiang, William J. Dally Computer System Laboratory Stanford University John Kim.

1 Lecture 25: Interconnection Networks Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix E) Review session,

1 Near-Optimal Oblivious Routing for 3D-Mesh Networks ICCD 2008 Rohit Sunkam Ramanujam Bill Lin Electrical and Computer Engineering Department University.

Low-Latency Virtual-Channel Routers for On-Chip Networks Robert Mullins, Andrew West, Simon Moore Presented by Sailesh Kumar.

Dragonfly Topology and Routing

Performance and Power Efficient On-Chip Communication Using Adaptive Virtual Point-to-Point Connections M. Modarressi, H. Sarbazi-Azad, and A. Tavakkol.

1 Lecture 23: Interconnection Networks Topics: Router microarchitecture, topologies Final exam next Tuesday: same rules as the first midterm Next semester:

Communication issues for NOC By Farhadur Arifin. Objective: Future system of NOC will have strong requirment on reusability and communication performance.

Elastic-Buffer Flow-Control for On-Chip Networks

Networks-on-Chips (NoCs) Basics

SMART: A Single- Cycle Reconfigurable NoC for SoC Applications -Jyoti Wadhwani Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramaniam,

High-Level Interconnect Architectures for FPGAs An investigation into network-based interconnect systems for existing and future FPGA architectures Nick.

DUKE UNIVERSITY Self-Tuned Congestion Control for Multiprocessor Networks Shubhendu S. Mukherjee VSSAD, Alpha Development Group.

High-Level Interconnect Architectures for FPGAs Nick Barrow-Williams.

1 Message passing architectures and routing CEG 4131 Computer Architecture III Miodrag Bolic Material for these slides is taken from the book: W. Dally,

Network-on-Chip Introduction Axel Jantsch / Ingo Sander

1 Lecture 26: Networks, Storage Topics: router microarchitecture, disks, RAID (Appendix D) Final exam: Monday 30 th Apr 10:30-12:30 Same rules as the midterm.

CS 8501 Networks-on-Chip (NoCs) Lukasz Szafaryn 15 FEB 10.

© Sudhakar Yalamanchili, Georgia Institute of Technology (except as indicated) Switch Microarchitecture Basics.

1 Lecture 15: Interconnection Routing Topics: deadlock, flow control.

Interconnect simulation. Different levels for Evaluating an architecture Numerical models – Mathematic formulations to obtain performance characteristics.

Interconnect simulation. Different levels for Evaluating an architecture Numerical models – Mathematic formulations to obtain performance characteristics.

Yu Cai Ken Mai Onur Mutlu

Lecture 16: Router Design

Interconnect Networks Basics. Generic parallel/distributed system architecture On-chip interconnects (manycore processor) Off-chip interconnects (clusters.

Intel Slide 1 A Comparative Study of Arbitration Algorithms for the Alpha Pipelined Router Shubu Mukherjee*, Federico Silla !, Peter Bannon $, Joel.

1 Lecture 22: Router Design Papers: Power-Driven Design of Router Microarchitectures in On-Chip Networks, MICRO’03, Princeton A Gracefully Degrading and.

Virtual-Channel Flow Control William J. Dally

1 Lecture 24: Interconnection Networks Topics: communication latency, centralized and decentralized switches, routing, deadlocks (Appendix F)

Predictive High-Performance Architecture Research Mavens (PHARM), Department of ECE The NoX Router Mitchell Hayenga Mikko Lipasti.

Network On Chip Cache Coherency Final presentation – Part A Students: Zemer Tzach Kalifon Ethan Kalifon Ethan Instructor: Walter Isaschar Instructor: Walter.

Flow Control Ben Abdallah Abderazek The University of Aizu

1 Lecture 22: Interconnection Networks Topics: Routing, deadlock, flow control, virtual channels.

How to Train your Dragonfly

The network-on-chip protocol

Lecture 23: Interconnection Networks

Azeddien M. Sllame, Amani Hasan Abdelkader

Lecture 23: Router Design

Lecture: Interconnection Networks

Low-Latency Virtual-Channel Routers for On-Chip Networks Robert Mullins, Andrew West, Simon Moore Presented by Sailesh Kumar.

Lecture: Interconnection Networks

CS 6290 Many-core & Interconnect

Chapter 2 Switching.

Lecture 25: Interconnection Networks

A Case for Bufferless Routing in On-Chip Networks

Presentation transcript:

Author : Jing Lin, Xiaola Lin, Liang Tang Publish Journal of parallel and Distributed Computing MAKING-A-STOP: A NEW BUFFERLESS ROUTING ALGORITHM FOR ON-CHIP NETWORK

OUTLINE Some background Virtual channel wormhole switching MAS Microarchitecture Evaluation Simulation results

VIRTUAL CHANNEL A channel designation which differs from that of the actual radio channel (or range of frequencies) on which the signal travels

WORMHOLE SWITCHING Large network packets are broken into small pieces called flits (flow control digits). The first flit, called the header flit holds information about this packet's route (namely the destination address) and sets up the routing behavior for all subsequent flits associated with the packet. The head flit is followed by zero or more body flits, containing the actual pay load of data. The final flit, called the tail flit, performs some book keeping to close the connection between the two nodes. One thing special about wormhole flow control is the implementation of virtual channels.

PROBLEM buffer routing need more power and area and also adds the complexity of on-chip network design.

MAKE A STOP 藉由增設一動態 register 來給 flits stop 以取代 buffers 並減少 deflected

Arbitration unit register array switch crossbar

Router has five input ports and five output ports Warm-up period of 100,000 cycles 10,000 packets are injected per node

TRAFFIC PATTERNS OR traffic assumes each node uniformly injects packets to randomly distributed destinations in the network. In TR traffic, the node ( i, j ) only communicates with node ( j, i ). In HS traffic, four hotspot nodes are located at the center of the network. The 80% of traffic is sent to randomly distributed destinations in the network, while the remaining traffic is to the hotspot nodes.

LATENCY Packet latency is calculated from the time when the first flit of a packet is generated, to the time when its last flit is ejected at the destination, including source queueing time.

the average hop count per packet as a function of injected rate under different synthetic traffic patterns before network saturates.

The power by flits traversing through the channels + the power needed by the switches in the router.