Work in Progress --- Not for Publication 1 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting ITRS/ERD ITWG Working Group FxF Meeting Maturity Evaluation for Selected Beyond CMOS Emerging Technologies Jim Hutchby - Facilitating San Francisco Marriott Hotel 55 Fourth Street, San Francisco, CA Nob Hill D Room Yerba Buena Level Sunday, July 13 9:00 a.m. – 5:45 p.m

Work in Progress --- Not for Publication 2 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting  Hiroyugi AkinagaAIST  Tetsuya AsaiHokkaido U.  Yuji AwanoFujitsu  George BourianoffIntel  Michel BrillouetCEA/LETI  Joe BrewerU. Florida  John CarruthersPSU  Ralph CavinSRC  U-In ChungSamsung  Philippe CoronelST Me  Shamik DasMitre  Erik DeBenedictisSNL  Simon Deleonibus LETI  Kristin De MeyerIMEC  Michael FrankAMD  Christian GamratCEA  Mike GarnerIntel  Dan HammerstromPSU  Wilfried HaenschIBM  Tsuyoshi HasegawaNIMS  Shigenori HayashiMatsushita  Dan HerrIBM  Toshiro HiramotoU. Tokyo  Matsuo HidakaISTEK  Jim HutchbySRC  Adrian IonescuETH  Kohei ItohKeio U.  Kiyoshi KawabataRenesas Tech  Seiichiro KawamuraSelete  Rick KiehlU. Minn  Hiroshi KotakiSharp  Atsuhiro KinoshitaToshiba  Franz KreuplQimonda  Nety KrishnaAMAT  Zoran KrivokapicAMD  Phil KuekesHP  Lou LomeIDA  Hiroshi MizutaU. Southampton  Murali Muraldihar Freescale  Fumiyuki NiheiNEC  Dmitri NikonovIntel  Wei-Xin NiNDL  Ferdinand PeperNICT  Yaw ObengNIST  Dave RobertsAir Products  Kaushal SinghAMAT  Sadas ShankarIntel  Thomas Skotnicki ST Me  Satoshi SugaharaTokyo Tech  Shin-ichi TakagiU. Tokyo  Ken UchidaToshiba  Yasuo WadaWaseda U.  Rainer WaserRWTH A  Franz Widdershoven NXP  Jeff WelserNRI/IBM  Philip WongStanford U.  Kojiro YagamiSony  David YehSRC/TI  In-Seok YeoSamsung  In-K YooSAIT  Peter ZeitzoffFreescale  Yuegang ZhangIntel  Victor ZhirnovSRC Emerging Research Devices Working Group

Work in Progress --- Not for Publication 3 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting Objectives  Workshop (For each of the seven technologies) –Receive expert inputs (pro & con) –Clarify status, potential, and remaining challenges –Formulate discussion/decision points to be considered in the Sunday ERD/TWG meeting  Emerging Research Devices Working Group Mtg. –Discuss and reach approximate consensus on potential & challenges for each technology –Reach approximate consensus on 1 or 2 “Beyond CMOS” technologies sufficiently mature to benefit from accelerated engineering development

Work in Progress --- Not for Publication 4 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting ERD “Beyond CMOS” Technology Selection Mtg Agenda – Sunday, July 13 9:00Welcome and Introductions Hutchby 9:10Background & ERD Meeting Objectives Hutchby 9:20Review Process for selecting 1 or 2 beyond CMOS emerging technologies 9:45Discuss Technologies 9:45NEMS Switch Technology 10:05Spin Torque Transfer Technology 10:25Carbon-based Nanoelectronics 10:45Break 11:00Atomic Switch / Electrochemical Metal Switch 11:20Collective Spin Devices (including M-QCA) 11:40Single Electron Transistors 12:00CMOL and FPNI 12:20Lunch (Working)

Work in Progress --- Not for Publication 5 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting ERD “Beyond CMOS” Technology Selection Mtg Agenda – Sunday, July 13 (Cont’d) 12:50Preliminary vote on technologies – Majority voting process 1:00Discuss preliminary results 1:45Second vote on technologies 2:00Discuss the one or two leading technologies resulting from vote 2:30Final vote on the leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and enhanced engineering development 2:45 Decide next steps in roadmapping the chosen technology(ies) 3:00Regular ERD Business Meeting 3:00 Planned ERD WorkshopsHutchby 3:15 ERD Device Workshop (Sept ) DiscussBourianoff 4:00 Summary of Nanoarchitecture ForumCavin 4:45 Review of ERM plans & coupling with ERDGarner 5:15Review definition of “Beyond CMOS”Hutchby 5:30Review Action ItemsHutchby 5:45Adjourn

Work in Progress --- Not for Publication 6 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting Process Proposed for Selecting “Beyond CMOS” Technology for Enhanced Engineering Development  Receive and evaluate White Papers from Proponents  Conduct an ERD Telecon to briefly review and discuss the White Papers to provide feedback prior to Workshop.  Receive proponent/opponent expert inputs on the candidate technologies on Saturday, July 12.  Select one or two candidate technologies via discussion, majority voting, and forming an approximate consensus on Sunday, July 13.  Report results to IRC on July 14 or 15.  Write a report by August 31.

Work in Progress --- Not for Publication 7 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting Decision Making & Majority Voting Scheme  Each member of ERD WG will be given a maximum of 3 votes to use in voting for their top 3 choices among the candidate technologies (Majority Voting scheme)  Only 0 or 1 vote can be cast for any candidate technology  Member does not have to use all 3 votes, but cannot use more than 3 votes.  All members can participate in the straw vote.  ERD WG members present in the July 12 Workshop & the July 13 FxF meeting will be eligible to vote at July 13 meeting.  The Candidate Technologies will be ordered according to which received the largest number of votes.  Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus.

Work in Progress --- Not for Publication 8 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting 2008 ERD Working Group Organization ERD SubcommitteesLeader(s) uChapter ChairHutchby uMemoryZhirnov uLogicBourianoff uArchitectureCavin uEditorsHutchby, Bourianoff, Cavin and Zhirnov uITRS Liaisons –PIDSNg, Hutchby –FEPHerr –Modeling & SimulationShankar –MaterialsShankar –MetrologyHerr –DesignYeh/Bourianoff –More than MooreBrillouet

Work in Progress --- Not for Publication 9 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting 2008 ERD Update Schedule  April 2 – Memory Workshop  April 2 – ERD Business Meeting  April 3 – 4 – ITRS Meetings (no public conference)  June ? – ERD Presentation draft for July 16 Conference due to Linda Wilson  July 10 – 11 Architecture Workshop & ERD Business Meeting  July 12 – ERD Business Meeting  July 14 – 15 – ITRS Meetings  July 16 – ITRS Public Conference  September 22 nd – Logic Workshop  September 23 rd – ERD Business Meeting?  August ? – ERD Chapter Update Material Due*  September ? – 2008 ITRS Update Content Frozen*  December 6 – 2009 ERD Chapter Kickoff Meeting in Seoul, Korea?  December 7 – 9 ITRS Meeting in Seoul, Korea  December 9 – ITRS Public Conference in Seoul, Korea  December 14 – 2009 ERD Chapter Kickoff Meeting in San * ERD typically uses the “update year” to prepare for the following “chapter re-write year (i.e. 2009” and does not provide an update.

Work in Progress --- Not for Publication 10 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting 2008 ERD/ERM Workshops Done

Work in Progress --- Not for Publication 11 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting Beyond CMOS – ERD/ERM Concepts, Definition proposals Jim Hutchby and T. Hiramoto Rev 6 06/27/08

Work in Progress --- Not for Publication 12 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting 2007 ITRS Executive Summary Fig 5 [updated for 2007] Traditional ORTC Models [Geometrical & Equivalent scaling] Scaling (More Moore) Functional Diversification (More than Moore) [2007 – add Definitions; Update Graphic] Continuing SoC and SiP: Higher Value Systems HV Power Passives

Work in Progress --- Not for Publication 13 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting 2007 ITRS “Moore’s Law and More” Alternative Definition Graphic Computing & Data Storage Heterogeneous Integration System on Chip (SOC) and System In Package (SIP) Sense, interact, Empower Baseline CMOS Memory RF HV Power Passives Sensors, Actuators Bio-chips, Fluidics “More Moore” “More than Moore” Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)

Work in Progress --- Not for Publication 14 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting 2008 ITRS “Beyond CMOS” Computing and Data Storage Beyond CMOS Source: Emerging Research Device Working Group “More Moore”“Beyond CMOS” 22nm16nm11nm8nm Baseline CMOS Ultimately Scaled CMOS Functionally Enhanced CMOS Spin Logic Devices Nanowire Electronics Ferromagnetic Logic Devices 32nm Channel Replacement Materials Low Dimensional Materials Channels Multiple gate MOSFETs New State Variable New Data Representation New Devices New Data Processing Algorithms

Work in Progress --- Not for Publication 15 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting year Beyond CMOS Elements ERD-WG in Japan Existing technologies New technologies Evolution of Extended CMOS

Work in Progress --- Not for Publication 16 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting year Beyond CMOS Elements Existing technologies New technologies Evolution of Extended CMOS ERD-WG in Japan

Work in Progress --- Not for Publication 17 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting “Beyond CMOS” Definition “Beyond CMOS” refers to emerging research devices, focused on a “new switch*” used to process information, typically exploiting a new state variable to provide functional scaling substantially beyond that attainable by ultimately scaled CMOS. Substantial scaling beyond CMOS is defined in terms of functional density, increased performance, dramatically reduced power, etc. Examples of Beyond CMOS include: a) molecular electronic devices, b) spin-based transistors and devices, c) ferromagnetic logic, etc. *The “New Switch” refers to an “information processing element or technology”, which is associated with compatible storage or memory and interconnect functions.

Work in Progress --- Not for Publication 18 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting Action Items (1/2) 1.Consider to include in the 2009 ERD Chapter the new chart entitled “Evolution of Extended CMOS” contributed by ERD Japan. BourianoffIn Process 2.Strengthen ties between US-EU-Asia. Requires good balance of representing members from three regions HutchbyIn Process 3.The best demonstrated parameters are obtained from different devices. Is it possible to obtain them simultaneously on one device? We should include a note to this effect. Bourianoff, Zhirnov 4.Extend the Mission of ERD to include additional Research Vectors proposed by the Japan ERD WG. These are Numbers 1 – 4 listed in Item No. 1 above. Bourianoff 5.Consider moving to PIDS in 2009: 1) III-V Alternate Channel Materials, and 2) Low Dimensional Materials. Discuss this with PIDS. (This discussion has begun.) BourianoffIn Process 6.Make the mission of ERD clear. Make it more Globally justified.Hutchby 7. Organize an ERD Working Group in KoreaIn U. ChungIn Process

Work in Progress --- Not for Publication 19 ERD WG 7/12-13/08 San Francisco Workshop & FxF Meeting Action Items (2/2) 8.Bob Doering argued that the Critical Evaluation Chart gives the wrong message; a.We need to re-think this chart b.This chart assigns a different meaning to red than is used by all the other ITRS chapters. The other chapters use red to highlight a major research gap. c.We should point the directions into which “critical path” research should be directed. We need a way to distinguish a Fundamental Limit versus the Maturity of the Technology Entry Hutchby 9.Need a dialog with the Design and Systems Drivers ITWG to address synergy between the two chapters. Hutchby, Bourianoff, Yeh In Process 10.Discuss/decide upon expanding scope to include Sensors, Actuators, and Power Sources to encompass More than Moore or Functional Diversification Hutchby and Brillouet 11.Discuss other materials (in addition to NiO) for Fuse/Anti-fuse Memory Tech Zhirnov & Garner 12.Plan Memory FXF Meeting in Germany for April 2, Include Memory Expert Panel. ZhirnovDone 13.Write paper/proposal for NSF Funding for workshops.Hutchby/ZhirnovDone 14.Include Akinaga-san in Memory Working GroupZhirnovDone