CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout techniques

CMOS Analog Design Using All-Region MOSFET Modeling 2 Simplified CMOS process flow p-type substrate STI (b) STI Nitride Photoresist p-type substrate (a) Oxide Photo- resist Poly STI p-type substrate STI p-well n-well (d) Photo- resist Poly p-type substrate p-welln-well (c) STI n + poly p + poly n+n+ n+n+ p+p+ p+p+ p-type substrate p-well n-well STI (e) Oxide spacer n + poly p + poly n+n+ n+n+ p+p+ p+p+ p-type substrate STI p- well n-well STI (f) Oxide spacer p + poly n+n+ n+n+ p+p+ p+p+ p-type substrate STI p-well n- well STI (g) n + poly

CMOS Analog Design Using All-Region MOSFET Modeling 3 CMOS structure Triple-well process p-substrate deep n-well n-well p-well n+n+ n+n+ p+p+ p+p+ Transistors in deep- submicron process

CMOS Analog Design Using All-Region MOSFET Modeling nm technology node nMOSpMOS Supply voltage V Thin oxide3 nm L gate 130 nm150 nm VTVT 0.3 V (130 nm)-0.24 V (150 nm) I Dsat (1.5V) 0.94 mA/  m0.42 mA/  m I off 3 nA/  m g msat 860 mS/mm430 mS/mm C j (0V) 0.65 fF/  m fF/  m 2 Silicide ( S, D and poly)  /sq Parameters of a six-metal-layer 180-nm CMOS technology node

CMOS Analog Design Using All-Region MOSFET Modeling 5 Integrated resistors h L W In the general case

CMOS Analog Design Using All-Region MOSFET Modeling 6 Resistivity of some metals Metal (bulk)Resistivity at 20 o CTCR Aluminum 2.8 ·  -cm 3800 ppm/ o C Copper 1.7 ·  -cm 4000 ppm/ o C Gold 2.4 ·  -cm 3700 ppm/ o C Sheet resistance of a copper layer of 1000 nm depth

CMOS Analog Design Using All-Region MOSFET Modeling 7 Polysilicon resistors CMOS Analog Design Using All-Region MOSFET Modeling 7

8 Summary of resistors in CMOS technology Resistor typeSheet resistance (  /sq) Temperature coefficient (ppm/ o C) Voltage coefficient (ppm/V) n + Polysilicon p + Polysilicon n + / p + Polysilicon (silicided) 5 n + Diffusion p + Diffusion n-Well

CMOS Analog Design Using All-Region MOSFET Modeling 9 The MOS transistor as a resistor Example: Verify that, in strong inversion, the equivalent resistance between source and drain of an MOS transistor at V DS =0 is given by V Q is the dc potential at the source.

CMOS Analog Design Using All-Region MOSFET Modeling 10 Metal-insulator-metal capacitors (a) Substrate C1C1 C2C2 C3C3 C parasitic C=C 1 +C 2 +C 3 Metal 1 Metal 2 Metal 3 Metal 4 Top view Cross section (b) ( a) vertical parallel plate structure, (b) lateral flux capacitor.

CMOS Analog Design Using All-Region MOSFET Modeling 11 Metal-oxide semiconductor capacitors (a) Poly-semiconductor (b) poly-poly capacitors VCC is typically around 100 ppm/V TCC is of the order of 20 ppm/ o C.

CMOS Analog Design Using All-Region MOSFET Modeling 12 MOSFET gate capacitors - 1 Gate capacitors in a p-well CMOS technology

CMOS Analog Design Using All-Region MOSFET Modeling 13 MOSFET gate capacitors - 2 experiment theory

CMOS Analog Design Using All-Region MOSFET Modeling 14 Intrinsic capacitances of the MOS transistor for V DS =0 MOSFET gate capacitors - 3 In accumulation In strong inversion

CMOS Analog Design Using All-Region MOSFET Modeling 15 In accumulation In inversion, a similar expression holds MOSFET gate capacitors - 4

CMOS Analog Design Using All-Region MOSFET Modeling 16 Summary of capacitors in CMOS CMOS Analog Design Using All-Region MOSFET Modeling 16 Capacitor typeCapacitance per unit area ( aF/  m 2 ) Temperature coefficient (ppm/  C) Voltage coefficient (ppm/V) MOM MOM (combined lateral and vertical structure) MOS gate (biased) MOS (heavily doped Si option) MIM (thin oxide option) Poly-poly

CMOS Analog Design Using All-Region MOSFET Modeling 17 Inductors Example: Inductance of a 5- turn spiral inductor with an average radius of 50  m. Planar spiral inductor

CMOS Analog Design Using All-Region MOSFET Modeling 18 Bipolar transistors (BJTs) in CMOS Flow of carriers in the CMOS-compatible bipolar junction transistor

CMOS Analog Design Using All-Region MOSFET Modeling 19 BJTs in triple-well CMOS

CMOS Analog Design Using All-Region MOSFET Modeling 20 Latchup Parasitic bipolar transistors in CMOS technology which may lead to latchup. (a) Cross section of the CMOS structure; (b) Equivalent circuit of the parasitic bipolar transistors and resistors

CMOS Analog Design Using All-Region MOSFET Modeling 21 Optical lithography - 1 Wafer Mask Photoresist Ultraviolet light

CMOS Analog Design Using All-Region MOSFET Modeling 22 SourceWavelength (nm) Intended resolution (nm) Year of introduction G-line * I-line * KrF laser ArF laser F 2 laser15765** *Filtered spectral components of high-pressure Hg or Hg-rare gas discharge lamps. ** The technology was abandoned. Optical lithography - 2 Wavelength used for optical lithography

CMOS Analog Design Using All-Region MOSFET Modeling 23 Optical lithography - 3 Optical proximity correction (OPC) counteracts lithography distortions

CMOS Analog Design Using All-Region MOSFET Modeling 24 MOSFET layout - 1 Mask layout and cross section of a CMOS inverter. N-well and P-well contacts not shown. Dashed lines represent metal connections

CMOS Analog Design Using All-Region MOSFET Modeling 25 Source/drain implant Shaded region Asymmetry MOSFET layout - 2 Diagonal shift in the source drain regions of a transistor due to a tilted implant

CMOS Analog Design Using All-Region MOSFET Modeling 26 NoNo Rule 1Same structure 2Same shape, same size 3Same orientation 4Same surroundings 5Minimum distance 6Common-centroid geometries 7Same temperature Rules for minimizing systematic mismatch of integrated devices MOSFET layout - 3

CMOS Analog Design Using All-Region MOSFET Modeling 27CMOS Analog Design Using All-Region MOSFET Modeling 27 Matching improvement by the addition of dummy devices for the layout of two resistors with a resistance ratio of 2/1: (a) unconnected dummy resistors (b) connected dummy resistors Unconnected dummy Conn. dummy MOSFET layout - 4

CMOS Analog Design Using All-Region MOSFET Modeling 28 (a) C ox C ox +  C ox C ox +2  C ox C ox +3  C ox A B A B A B B A (b) MOSFET layout - 5 Mock layouts of some possible common-centroid geometries for improved matching. Transistors with the same label are connected in parallel.

CMOS Analog Design Using All-Region MOSFET Modeling 29 A differential pair with a folded layout AB C DE AB C DE C DE AB MOSFET layout - 6

CMOS Analog Design Using All-Region MOSFET Modeling 30 AB C DE F G C D E A B F G B A G F C DE MOSFET layout - 7 A third device is added to the differential pair without degrading the symmetry of the layout

CMOS Analog Design Using All-Region MOSFET Modeling 31 Common-centroid layout of a differential pair. CMOS Analog Design Using All-Region MOSFET Modeling 31 A B D E C A C B E D C MOSFET layout - 8

CMOS Analog Design Using All-Region MOSFET Modeling 32 Current mirror with an attenuation factor of 16: (a) Schematic; (b) Mock layout. I in (b) I out I in (a) MOSFET layout - 9