Kuang-Yu,Li 2013 IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM Kuang-Yu, Li Department of Electronics Engineering National.

Slides:

Advertisements

Similar presentations

TDC130: High performance Time to Digital Converter in 130 nm

Advertisements

Reconfigurable Computing (EN2911X, Fall07) Lecture 04: Programmable Logic Technology (2/3) Prof. Sherief Reda Division of Engineering, Brown University.

Mixed Signal Chip Design Lab CMOS Analog Addition/Subtraction Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania.

Robust Low Power VLSI R obust L ow P ower VLSI Sub-threshold Sense Amplifier (SA) Compensation Using Auto-zeroing Circuitry 01/21/2014 Peter Beshay Department.

Accelerating DRAM Performance

18/05/2015 Calice meeting Prague Status Report on ADC LPC ILC Group.

Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004.

Praveen Venkataramani Suraj Sindia Vishwani D. Agrawal FINDING BEST VOLTAGE AND FREQUENCY TO SHORTEN POWER CONSTRAINED TEST TIME 4/29/ ST IEEE VLSI.

Custom Implementation of DSP Systems School of Electrical and

Introduction to CMOS VLSI Design Clock Skew-tolerant circuits.

Ultra Low Power PLL Implementations Sudhanshu Khanna ECE

1/42 Changkun Park Title Dual mode RF CMOS Power Amplifier with transformer for polar transmitters March. 26, 2007 Changkun Park Wave Embedded Integrated.

Chapter 9 Memory Basics Henry Hexmoor1. 2 Memory Definitions  Memory ─ A collection of storage cells together with the necessary circuits to transfer.

Lecture 8: Clock Distribution, PLL & DLL

Die-Hard SRAM Design Using Per-Column Timing Tracking

Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun.

Programmable logic and FPGA

Introduction to Analog-to-Digital Converters

Phase Locked Loops Continued

A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling Dian Huang Ying Qiao.

Wireless RF Receiver Front-end System – Wei-Liang Chen Wei-Liang Chen Wireless RF Receiver Front-end System Yuan-Ze University, VLSI Systems Lab

DDR SDRAM ASIC Course Saeed Bakhshi May 2004 Class presentation based on ISSCC2003 paper: A 1.8V, 700Mb/s/pin, 512Mb DDR-II SDRAM with On-Die Termination.

Motivation Yang You 1, Jinghong Chen 1, Datao Gong 2, Deping Huang 1, Tiankuan Liu 2, Jingbo Ye 2 1 Department of Electrical Engineering, Southern Methodist.

Robust Low Power VLSI Selecting the Right Conference for the BSN FIR Filter Paper Alicia Klinefelter November 13, 2011.

TOF Electronics Qi An Fast Electronics Lab, USTC Sept. 16~17, 2002.

A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group.

© H. Heck 2008Section 4.41 Module 4:Metrics & Methodology Topic 4: Recovered Clock Timing OGI EE564 Howard Heck.

Chapter 13 Linear-Digital ICs. Copyright ©2009 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. Electronic Devices.

1 Process-Variation Tolerant Design Techniques for Multiphase Clock Generation Manohar Nagaraju +, Wei Wu*, Cameron Charles # + University of Washington,

Mehdi Sadi, Italo Armenti Design of a Near Threshold Low Power DLL for Multiphase Clock Generation and Frequency Multiplication.

An Ultra Low Power DLL Design

A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology

1.  Why Digital RF?  Digital processors are typically implemented in the latest CMOS process → Take advantages scaling. (e.g. density,performance) 

Company LOGO High Performance Processors Miguel J. González Blanco Miguel A. Padilla Puig Felix Rivera Rivas.

Design of Front-End Low-Noise and Radiation Tolerant Readout Systems José Pedro Cardoso.

Introduction As the explosive growth in complexity of integrated circuits, system-on-a-chip (SoC) had become a design trend for increasing the operating.

S.Manen– IEEE Dresden – Oct A custom 12-bit cyclic ADC for the electromagnetic calorimeter of the International Linear Collider Samuel.

A 240ps 64b Carry-Lookahead Adder in 90nm CMOS Faezeh Montazeri Advanced VLSI Course Presentation University of Tehran December.

CPEN Digital System Design

1 ECE1352F – Topic Presentation - ADPLL By Selvakkumaran S.

Delay Locked Loop with Linear Delay Element

Departement Elektriese, Elektroniese & Rekenaar-Ingenieurswese Department of Electrical, Electronic & Computer Engineering Kgoro ya Merero ya Mohlagase,

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation Keng-Jan Hsiao and Tai-Cheng Lee National Taiwan University Taipei, Taiwan.

1 A Frequency Synthesizer Using Two Different Delay Feedbacks 班級：積體所碩一學生：林欣緯指導教授：林志明教授 Circuits and Systems, ISCAS IEEE International Symposium.

ICECS 2010 First Order Noise Shaping Time-to-Digital Converter

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Improved Effective Phase Resolution Chang-Kyung Seong 1), Seung-Woo Lee.

LC Voltage Control Oscillator AAC

MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit December 5th, 2005 Low Emission Digital Circuit Design Junfeng Zhou.

A 1-V 2.4-GHz Low-Power Fractional-N Frequency Synthesizer with Sigma-Delta Modulator Controller 指導教授 : 林志明教授學生 : 黃世一 Shuenn-Yuh Lee; Chung-Han Cheng;

Yi-Lin, Tu 2013 IEE5011 –Fall 2013 Memory Systems Wide I/O High Bandwidth DRAM Yi-Lin, Tu Department of Electronics Engineering National Chiao Tung University.

© 2003 Xilinx, Inc. All Rights Reserved Global Timing Constraints FPGA Design Flow Workshop.

Rad-Tolerant design of all-digital DLL Tuvia Liran ] Ran Ginosar ] Dov Alon ] Ramon-Chips.

McGill Increasing the Time Dynamic Range of Pulse Measurement Techniques in Digital CMOS Applications of Pulse Measurement: Duty-Cycle Measurement Pulsed.

Computer Architecture Lecture 32 Fasih ur Rehman.

111 Communications Fall 2008 NCTU EE Tzu-Hsien Sang.

1 A High-Speed and Wide Detectable Frequency Range Phase Detector for DLLs Babazadeh, H.; Esmaili, A.; Hadidi, K.; NORCHIP, 2009 Digital Object Identifier:

Shih-Fan, Peng 2013 IEE5008 –Autumn 2013 Memory Systems DRAM Controller for Video Application Shih-Fan, Peng Department of Electronics Engineering National.

DEFENSE EXAMINATION GEORGIA TECH ECE P. 1 Fully Parallel Learning Neural Network Chip for Real-time Control Jin Liu Advisor: Dr. Martin Brooke Dissertation.

A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group Department of.

1 The Link-On-Chip (LOC) Project at SMU 1.Overview. 2.Status 3.Current work on LOCs6. 4.Plan and summary Jingbo Ye Department of Physics SMU Dallas, Texas.

Delay-based Spread Spectrum Clock Generator Subramaniam Venkatraman Matthew Leslie University of California, Berkeley EE 241 Final Presentation May 9 th.

5 Gbps J. SMU 1 A Serializer for LAr Front-end electronics upgrade 1.Requirements and design philosophy. 2.Key features of the serializer.

Phase-Locked Loop Design PREPARED BY:- HARSH SHRMA ( ) PARTH METHANIYA ( ) ARJUN GADHAVI ( ) PARTH PANDYA (

1 D. BRETON 1, L.LETERRIER 2, V.TOCUT 1, Ph. VALLERAND 2 (1) LAL ORSAY - France (2) LPC CAEN - France Super Nemo Absolute Time Stamper A high resolution.

Electronic Devices and Circuit Theory

Hugo Furtado CERN - Microelectronics Group 11th Workshop on Electronics for LHC and future Experiments Delay25, an ASIC for timing adjustment in LHC Delay25.

End OF Column Circuits – Design Review

Chapter 13 Linear-Digital ICs

Low Jitter PLL clock frequency multiplier

MCP Electronics Time resolution, costs

Presentation transcript:

Kuang-Yu,Li 2013 IEE5011 –Autumn 2013 Memory Systems Duty Cycle Correctors (DCC) In GDDR5 SDRAM Kuang-Yu, Li Department of Electronics Engineering National Chiao Tung University

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Outline Introduction Basics  DCC and GDDR5 Comparison  Analog and Digital DCC All-Digital DCC DCC in GDDR5 Conclusion 2

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Introduction GDDR5 AMD first shipped in 2008 Sony used in

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (1/4) 4

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (2/4) Pre-fetch of 8 Array Bank Grouping New training and tracking New Clocking 5

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (3/4) Data strobe signal (DQS)~>Write data clock(WCK) CK x 1, WCK x2, Data x4 6

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic GDDR5 (4/4) 7 [1]

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basics DCC (1/3) Why do we need Duty-Cycle-Correctors ? Improve valid data window Reduce duty cycle error 8

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic DCC (2/3) Corrects input to 50% duty-cycle Two functions: Detect  define 50% boundary Correct  adjust edge until correct 9

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Basic DCC (3/3) Design : Location –on/off path Integration -embedded or not Locking time Operating frequency range Offset -comes from detector Implementation -analog or digital Other (power, area…) 10

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog DCC Simple negative feedback 11

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog DCC :Detector Integrating Error 12

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog DCC :Corrector Cross-coupled differential pair 13

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Digital DCC Simple negative feedback 14

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Digital DCC :Detector Detection Loop Time-mutiplexing between clocks Integrated error and amplified 15

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Digital DCC :Corrector Chargepump :offset adjusting 16

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Analog and Digital Comparison Digital DCC is preferred! Power,range,function,supply, mismatch 17 AnalogDigital DCC sharingXV Common mode Variation InsensitiveSensitive Correction rangeNarrowWide Power EfficientXV Manual overrideXV [2]

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li All-Digital DCC(ADDCC) Wide-range, high resolution Combined with DLL Low jitter and fast lock time Open loop scheme 18 DLL_out [3]

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li ADDCC: Timing Rising of DLL_out and Hclk Phase error ε,WSG delay α 19

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li ADDCC: Cycle Detector Dual delay line with WSG Overcoming trade-offs Small Overhead 20

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result 21 Process0.18um CMOS Operating frequency440MHz~1.5GHz Supply1.8V Duty cycle ratio50±2% Peak-to Peak Maximum lock-in timeADDCC:5 cycles Area0.053mm % -->

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li GDDR5 Clock Distribution P:PLL,G:Global Driver DQ Pad 22

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 Wide-range, fast-lock, offset tolerant [5]  Anti-harmonic binary search(ABS) CML and PLL in clock distribution 23

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :Adjuster Between Rx and Driver Off clock-path –jitter free 4 phase clock 24 Step: 6ps Range: ±100ps

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :Detector Switch,ABS circuit, 2 latches, comparator To adder based counter -> Adjuster 25

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :Detection Methodology iclk vs. qclk and qclk vs. iclkb 26

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 :ABS Circuit Weighted Delay Cell and range adjuster Anti-harmonic and wide frequency range 27

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result Operating frequency and correction range 28

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result :Locking Time Five input clock ranges 29

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Measured Result :Locking process 30

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Chip Microphotograph mm 2 31

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li DCC in GDDR5 Summary 32 Process54m CMOS triple-metal Operating frequency800MHz~3.5GHz (1.6 GHz~7 GHz) Supply1.5V Correction range-100ps ~ +100ps Step resolution6ps Lock-in timeMin:64 cycles Max:256 cycles Area0.017mm 2

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Conclusion Digital DCC in state of the art DRAM design is necessary and important DCC in GDDR5 with wide-range fast-lock duty-cycle corrector with offset-tolerant capability WCK is up to 3.5GHz to sustain 7Gbps/pin 33

NCTU IEE5011 Memory Systems 2013Kuang-Yu,Li Reference [1] Kho, R,et.al, “A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques”, IEEE Journal of Solid-State Circuits, vol.45,no.1,pp , Jan. 2010Kho, RSolid-State Circuits, vol.45,no.1 [2] L. Raghavan et.al, “Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link,” VLSI Design, pp ,Jan.2010Raghavan et.al, VLSI Design [3] Dongsuk Shin et.al, “A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC”, ISSCC,pp , Feb. 2007Dongsuk ISSCC [4] Shao-Ku Kao et.al, “All-Digital Fast-Locked Synchronous Duty-Cycle Corrector” IEEE Transactions on Circuits and Systems,vol.53,pp , Dec. 2006Shao-Ku KaoCircuits and Systems [5] Dongsuk Shin, Kwang-Jin Na et.al, “Wide-Range Fast-Lock Duty-Cycle Corrector with Offset-Tolerant Duty-Cycle Detection Scheme for 54nm 7Gb/s GDDR5 DRAM Interface,” Symposium on VLSI Circuits Digest of Technical Papers,pp , June 2009 [6] Kyung Hoon Kim et.al, “A 5.2Gb/p/s GDDR5 SDRAM with CML Clock Distribution Network”, ESSCIRC,pp , Sept. 2008Kyung Hoon Kim ESSCIRC 34