Prof Csaba Andras Moritz http://www.ecs.umass.edu/ece/andras ECE 353 Lab B Prof Csaba Andras Moritz http://www.ecs.umass.edu/ece/andras

Brief Intro of Instructor Research Background Class related stuff http://ece353.ecs.umass.edu Labs B and D Office hours Tue-Th 2-3PM Or send email for appointment

Outline Lab B Overview Demo by UGAs

In this lab, you will… Design and implement a serial MIDI receiver Hardware in an Altera Complex Programmable Logic Device (CPLD) MAX 7000S (part number EPM7064SLC44-10) Coding in Verilog Using ALTERA Quartus II software tools for synthesis Wire up and program on board MIDI signal from PC Musical notes played using PC keyboard & MIDI OX sw Debug - functional simulation (wave forms) Debug of board - logic analyzer

MIDI Musical Instrument Digital Interface Developed in 1980s Common hardware interface and protocol Allows electronic musical devices to communicate with each other MIDI messages are transmitted asynchronously Like UART – Universal Asynchronous Receiver Transmitter UART is more flexible with many parameters time bit 0 bit 1 bit n-1 no char start stop ...

MIDI Specification Groups of bytes, typically three Each byte with START and STOP bit Status – code for Note On, Off, other ctrl, ChID Data bytes – MSB bit is off (0) 2nd B: Note On or Off message with note number 128 different notes, 10 octaves 3rd B: Note On or Off with velocity (how hard is instr. pressed) STOP bit Idle MSB LSB START 1 2 3 4 5 6 7 Data word

Decoding of a MIDI Message In your work you will be decoding MIDI 31,250 bits/s fixed baud rate, bit time (BT) 32us With START & STOP a MIDI msg is 10BT, 320us You see this with wave form Consecutive frames separated by undefined time idle @1.5 BT @8.5 BT stop start start 8 bits stop @2.5 BT frame 3 frame 2 frame 1

Decoding of MIDI (contd.) Board has a 4MHz clock that you need to divide Before a frame, signal line is high The receive must wait for 0 and detect neg edge Now start sampling 8 bits (payload) in the middle See below at 1.5BT, …8.5BT Stop at 9.5 BT, that is the STOP bit Repeat for each byte idle @1.5 BT @8.5 BT stop start start 8 bits stop @2.5 BT frame 3 frame 2 frame 1

Decoding of MIDI (contd.) Sampled value at 9.5BT is not logic 1? A MIDI receiver sets a flag “Framing Error” You can implement if you want (not required) Sampling at least once per bit but commonly more times and vote A voter has a number of inputs and generates an output based on e.g., majority or plurality of inputs TMR (Triple Modulo Redundancy) voter would vote 1 if 2 out of 3 inputs are 1 A 5 input majority voter would need 3 out 5 A plurality voter needs a plurality (not majority)

How it Works, Circuit Schematic The MIDI OX sw transforms keyboard into an electronic music keyboard. MIDI signal is generated by the PC. MIDI OX will send a MIDI Note On message Cable terminated with an opto-isolator. The CPLD will be clocked by a 4MHz crystal oscillator, from which you may have to derive local clock for sampling. Output of CPLD drives 7 LEDs to display the note number.

Programming through JTAG JTAG - Joint Test Action Group: IEEE 1149.1 standard entitled: Standard Test Access Port and Boundary-Scan Architecture test access ports used for testing printed circuit boards (and chips) using boundary scan. Used also for programming embedded devices. Most FPGAs, PLDs are programmed via a JTAG port. JTAG ports commonly available in ICs Boundary scan, scan chains, mbist, logic bist connected Chips chained together with Jtag signals and connected to main JTAG interface on PCB

Design in Verilog A quick overview follows Acknowledgements: Some information builds on an internal course at BlueRISC, 2009 Papers by Clifford Cummings – SNUG-2000 Please check links on the web for free Verilog references for refreshing your Verilog skills in more depth

Translating Algorithms to Designs Divide and conquer Break into smaller ‘black-boxes’ when complicated Think also about performance – what you do in a clock period Focus on the heart of the problem first Stub-out all (or majority of) modules List inputs, outputs Write comments - how outputs can be generated from inputs Implement one by one Control-first design is intuitive for ordering your work FSMs, state-based outputs, output generation logic Verification Instantiate and wire together in top module

Example for Breaking Up

Example Design – Pieces Implemented in Modules Courtesy BlueRISC Inc

Modules Defines ‘black-box’ piece of hardware May be instantiated in other modules Can instantiate other modules

Blocks in Modules forever always initial Commonly used, synthesizable Evaluated whenever a signal in sensitivity list changes in simulator Evaluated regardless of sensitivity list in actual hardware initial Commonly used, non-synthesizable Useful for testbench creation Setting initial conditions else triggered by external events forever Commonly used for generating clocks forever clk = #5 ~clk;

Combinatorial vs. Sequential Blocks Generate signals inside a clock E.g., signal_nxt Sequential Latch signal values on clock edges E.g., signal

Basic Value Manipulations

State Machines Note: at BlueRISC, we would call “next” “state_nxt”

Variables in Hardware – Adder Example //sequential part, uses sum_out_nxt //Created in the above block from sum_out

Sensitivity Lists Simulation depends on list // simulation matches synthesis always@(a or b) out=a&b; // simulation fails to match synthesis when ‘a’ toggles always@(b) Consider that ‘a’ and ‘b’ are driven by independent logic (say, with different clocks). The flaw in the second block may give false positive for testing an implemented protocol when ‘a’ switches prior to ‘b’ and prior to evaluation of ‘out’ - likewise this may result in a false negative for otherwise good logic */ Synthesis does not depend on list Only exception is clock edges always@(posedge clk) if(reset)…else…

Blocking vs. Non-Blocking Statements First block non-blocking (NB) a,z updated after 5 time units Second block blocking (B) Evaluated in order Total time 6 units Value of b toggles 3 times

Coding Guidelines for B vs NB Use NB in always blocks for sequential logic, e.g., Use B in always blocks for combinational logic Otherwise pre-synthesis simulation might not match with that of synthesized circuit or has poor simulation performance // Good // Bad

Example - Shift-Register in Verilog Incorrect implementation always @(posedge clk) begin shift_reg[2] = shift_reg[3]; shift_reg[1] = shift_reg[2]; shift_reg[0] = shift_reg[1]; end * ‘=‘ : Blocking Assignment * Value in shift_reg[3] will be assigned to shift_reg[0] directly Correct implementation always @(posedge clk) begin shift_reg[2] <= shift_reg[3]; shift_reg[1] <= shift_reg[2]; shift_reg[0] <= shift_reg[1]; End * ‘<=‘ : Non-Blocking Assignment * Updating will happen after capturing all right-side register values

Simulation Simulation time not real REG_DELAY for sequential logic No gate delays All evaluations happen same time Zero time for combinatorial logic Time is “stopped” when needed How to simulate accurately re: synthesis results? REG_DELAY for sequential logic Register outputs are valid just after the clock edge Manual delay in simulation is inserted to mimic real world delay Illusion for passage of “time” in simulation

Verilog Debugging Testbenches Waveforms Verilog code to exercise your logic Waveforms Check signals and control-flow visually

Template You can use template to start coding /*-------------------------------------------------------------------- Copyright 2009, …. --------------------------------------------------------------------- Project: ECE353 Lab B Description : This module is a generic template starting point $Header: Exp $ Revision History Date Person Description 21/Aug/2009 C Andras Moritz Initial Version -------------------------------------------------------------------*/ module demo_template ( input clk, input reset, // INPUTS // OUTPUTS ); /*AUTOWIRE*/ // LOCAL REGs // PARAMETERS /* Combinatorial logic */ always@(/*AUTOSENSE*/) begin end Sequential logic always@(posedge clk) if(reset) else endmodule // demo_template You can use template to start coding Note: use AUTOSENSE if you are using emacs to help fill sensitivity list

More Details Please consult course website Also check deliverables for the Lab in the Lab review document Next Demo by the UGAs