Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Topics n Sequential machine (§5.2, §5.3) n FSM construction (§5.4) n Testing and design for testability (§4.8, §5.7) –Fault models –Combinational logic testing –Sequential logic testing

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Manufacturing Testing n Errors are introduced during manufacturing n Testing: manufacturing validation n Varieties of testing: –functional testing –performance testing (binning chips by speed) n Testing also weeds out infant mortality

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Fault Modeling n Fault model –Convert a physical problem to a logical problem –Stuck-at, stuck-open, delay... fault models –Single-fault assumption n With fault models +Simulate the I/O behavior produced by the fault +Find possible locations of faults –impossible to incorporate all manufacturing faults »Can’t guarantee the circuit is fault-free even if no fault is found under the fault model

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Stuck-at-0/1 Faults n Stuck-at-0/1 (s-a-0/1): a wire is always stuck at 0 or 1, independent of its drive value –Easiest and useful in practice, thus most popular 1 0B A C 0 1B A C 0 1B A C 1 0B A C

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Stuck-at-open/closed Model n Models transistors always on/off –how do we test t1 stuck-open?

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Delay Fault n Delay falls outside acceptable limits –gate delay fault model: »assume that all delays are lumped into one gate; –path delay fault models: »assume delay problems along path through network. n Delay problems reduce yield –performance problems; –functional problems in some types of circuits.

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Combinational Network Testing n Assume a combinational network Z(x); a fault f and the faulty network Z f (x) –Test vector: all the x that satisfies Z f  Z = 1 »Boolean satisfiability problem: NP complete n Testing procedure –Control: the primary inputs (i.e. set test vector) –Observe: the primary outputs –Compare: outputs with good circuit outputs

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Combinational Testing Example 1 Goal: test output of gate D for s-a-0 fault A B C D E F 0 i1 i2 i3 i4 i5 i6 O s-a

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Testing Procedure n Two major steps: –Propagate (forward): »set the internal lines so that the faulty value can be seen at the PO –Justify (backward) »set the PIs so that the internal lines can be justified n Reconvergent fanouts –make justification difficult

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Redundancy n If Z f  Z, there is no way to find the fault –Can’t justify n Redundancy causes Z f  Z –Z(x) = a + ab (s-a-1 for the a in ab) –Hard to completely remove redundancy a b Z s-a-1

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Sequential Testing n Much harder than combinational testing –Can’t set memory element elements directly –Can’t observe memory elements directly n Functional testing: FSM verification –Only a RT level description is need –Can also be used in design validation

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei FSM Verification n Given a sequential circuit S, how do we verify it actually is the FSM we want? –Initialization: bring S to a known state »E.g. “0” initializes the sequencer to state S0 –Verify S has (at least) n states »Given k flip-flops, can know S has at most 2 k states »If n = 2 k, can then verify S has n states –Verify every transition in the state table of S

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Sequence Recognizer Example Presentinputnextoutput S0 (00)0S0 (00)00 S0(00)1S1 (01)00 S1(01)0S0 (00)01 S1(01)1S2 (10)00 S2(10)0S0 (00)11 S2(10)1S2 (10) A A B A B C A A C A A

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Time-frame Expansion n Another way to look at FSM verification –Unroll machine in time –One SA fault becomes multiple faults

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Unreachable States n State assignment may cause some states to be unreachable –E.g. “11” in the sequence recognizer n FSM verification –Violate the maximum states assumption »E.g. The sequence recognizer would not tell the difference between a 1110/10 sequence recognizer n Time-frame expansion –Unable to set an internal value

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Design for Testability n Controllability: the ability to establish a specific signal value at each circuit node n Observability: the ability to determine the value at each circuit node n Scan registers –Increase controllability and observability for sequential circuits –LSSD (level-sensitive scan design), Scan-path

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Full Scan Method n Connect all the system flip-flops in a scan chain as a big shift register n When in “test” mode –Stop system clock –Scan in the value for each flip-flop in the chain –Run the system clock for one or more cycles –Scan out the value for each flip-flop in the chain

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Scan Chain Scan-in Scan-out

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei An LSSD Latch D1 CK1 CK2 CK3 D2 Q

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei A Multiplexed D Flip-flop DQ TE DQ D2 D1  Q

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Partial Scan n Full scan is expensive—must roll out and roll in state many times during a set of tests. n Partial scan selects some registers for scannability. n Requires analysis to choose which registers are best for scan.

Modern VLSI Design 3e: Chapter 5,6 Copyright  2002 Prentice Hall PTR Adapted by Yunsi Fei Boundary Scan n Board-level debugging scan_in scan_out