Modern VLSI Design 3e: Chapters 1-3 week12-1 Lecture 30 Scale and Yield Mar. 24, 2003.

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Presentation transcript:

Modern VLSI Design 3e: Chapters 1-3 week12-1 Lecture 30 Scale and Yield Mar. 24, 2003

Modern VLSI Design 3e: Chapters 1-3 week12-2 Scale In library

Modern VLSI Design 3e: Chapters 1-3 week12-3 Yield of fabrication process 1. System Yield: = Random Yield: A = chip area D = defective density 3. Total Yield:

Modern VLSI Design 3e: Chapters 1-3 week12-4 Example

Modern VLSI Design 3e: Chapters 1-3 week12-5 Lectures 31 and 32 Routing and simulation Mar. 26,28, 2003

Modern VLSI Design 3e: Chapters 1-3 week12-6 Topics Layouts for logic networks. Channel routing. Simulation.

Modern VLSI Design 3e: Chapters 1-3 week12-7 Standard cell layout Layout made of small cells: gates, flip- flops, etc. Cells are hand-designed. Assembly of cells is automatic: cells arranged in rows; wires routed between (and through) cells.

Modern VLSI Design 3e: Chapters 1-3 week12-8 Standard cell structure VDD VSS n tub p tub Intra-cell wiring pullups pulldowns pin Feedthrough area

Modern VLSI Design 3e: Chapters 1-3 week12-9 Standard cell design Pitch: height of cell. All cells have same pitch, may have different widths. VDD, VSS connections are designed to run through cells. A feedthrough area may allow wires to be routed over the cell.

Modern VLSI Design 3e: Chapters 1-3 week12-10 Single-row layout design Routing channel cell wireHorizontal track Vertical track height

Modern VLSI Design 3e: Chapters 1-3 week12-11 Routing channels Tracks form a grid for routing. Spacing between tracks is center-to-center distance between wires. Track spacing depends on wire layer used. Different layers are (generally) used for horizontal and vertical wires. Horizontal and vertical can be routed relatively independently.

Modern VLSI Design 3e: Chapters 1-3 week12-12 Routing channel design Placement of cells determines placement of pins. Pin placement determines difficulty of routing problem. Density: lower bound on number of horizontal tracks needed to route the channel. Maximum number of nets crossing from one end of channel to the other.

Modern VLSI Design 3e: Chapters 1-3 week12-13 Pin placement and routing before abc bca abc bca Density = 3 Density = 2

Modern VLSI Design 3e: Chapters 1-3 week12-14 Example: full adder layout Two outputs: sum, carry. sum carry x1 x2 n1 n2 n3 n4

Modern VLSI Design 3e: Chapters 1-3 week12-15 Layout methodology Generate candidates, evaluate area and speed. Can improve candidate without starting from scratch. To generate a candidate: place gates in a row; draw wires between gates and primary inputs/outputs; measure channel density.

Modern VLSI Design 3e: Chapters 1-3 week12-16 A candidate layout x1x2n1n2n3n4 a b c s cout Density = 5

Modern VLSI Design 3e: Chapters 1-3 week12-17 Improvement strategies Swap pairs of gates. Doesn’t help here. Exchange larger groups of cells. Swapping order of sum and carry groups doesn’t help either. This seems to be the placement that gives the lowest channel density. Cell sizes are fixed, so channel height determines area.

Modern VLSI Design 3e: Chapters 1-3 week12-18 Left-edge algorithm Basic channel routing algorithm. Assumes one horizontal segment per net. Sweep pins from left to right: assign horizontal segment to lowest available track.

Modern VLSI Design 3e: Chapters 1-3 week12-19 Example ABC ABBC

Modern VLSI Design 3e: Chapters 1-3 week12-20 Limitations of left-edge algorithm Some combinations of nets require more than one horizontal segment per net. BA AB aligned ?

Modern VLSI Design 3e: Chapters 1-3 week12-21 Vertical constraints Aligned pins form vertical constraints. Wire to lower pin must be on lower track; wire to upper pin must be above lower pin’s wire. BA AB

Modern VLSI Design 3e: Chapters 1-3 week12-22 Dogleg wire A dogleg wire has more than one horizontal segment. BA AB

Modern VLSI Design 3e: Chapters 1-3 week12-23 Rat’s nest plot Can be used to judge placement before final routing.

Modern VLSI Design 3e: Chapters 1-3 week12-24 Simulation Goals of simulation: functional verification; timing; power consumption; testability.

Modern VLSI Design 3e: Chapters 1-3 week12-25 Types of simulation Circuit simulation: analog voltages and currents. Timing simulation: simple analog models to provide timing but not detailed waveforms. Switch simulation: transistors as semi-ideal switches.

Modern VLSI Design 3e: Chapters 1-3 week12-26 Types of simulation, cont’d. Gate simulation: logic gates as primitive elements. Models for gate simulation: zero delay; unit delay; variable delay. Fault simulation: models fault propagation (more later).

Modern VLSI Design 3e: Chapters 1-3 week12-27 Example: switch simulation a + + b c d c X X X o 0 1 1

Modern VLSI Design 3e: Chapters 1-3 week12-28 Example, cont’d. a + + b c d c o

Modern VLSI Design 3e: Chapters 1-3 week12-29

Modern VLSI Design 3e: Chapters 1-3 week12-30