Comp Sci 251 -- vars & expns 1 Ch. 4 Variables and Expressions.

Slides:



Advertisements
Similar presentations
Lecture 13: 10/8/2002CS170 Fall CS170 Computer Organization and Architecture I Ayman Abdel-Hamid Department of Computer Science Old Dominion University.
Advertisements

Goal: Write Programs in Assembly
CWRU EECS 3221 Language of the Machine EECS 322 Computer Architecture Instructor: Francis G. Wolff Case Western Reserve University.
Integer Arithmetic: Multiply, Divide, and Bitwise Operations
Review of the MIPS Instruction Set Architecture. RISC Instruction Set Basics All operations on data apply to data in registers and typically change the.
1 ECE462/562 ISA and Datapath Review Ali Akoglu. 2 Instruction Set Architecture A very important abstraction –interface between hardware and low-level.
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 5: Data Transfer Instructions / Control Flow Instructions Partially adapted from Computer.
SPIM and MIPS programming
Fall EE 333 Lillevik 333f06-l4 University of Portland School of Engineering Computer Organization Lecture 4 Assembly language programming ALU and.
MIPS Assembly Language Programming
1 Computer Architecture MIPS Simulator and Assembly language.
The University of Adelaide, School of Computer Science
Assembly Language Working with the CPU.
1 COMS 361 Computer Organization Title: Instructions Date: 9/28/2004 Lecture Number: 10.
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 4: Arithmetic / Data Transfer Instructions Partially adapted from Computer Organization.
S. Barua – CPSC 440 CHAPTER 2 INSTRUCTIONS: LANGUAGE OF THE COMPUTER Goals – To get familiar with.
COMP3221: Microprocessors and Embedded Systems--Lecture 4 1 COMP3221: Microprocessors and Embedded Systems Lecture 4: Number Systems (II)
Lecture 5 Sept 14 Goals: Chapter 2 continued MIPS assembly language instruction formats translating c into MIPS - examples.
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Hao Ji.
Princess Sumaya Univ. Computer Engineering Dept. Chapter 2:
MIPS Instruction Set Advantages
Some material taken from Assembly Language for x86 Processors by Kip Irvine © Pearson Education, 2010 Slides revised 2/2/2014 by Patrick Kelley.
Summer 2014 Chapter 1: Basic Concepts. Irvine, Kip R. Assembly Language for Intel-Based Computers 6/e, Chapter Overview Welcome to Assembly Language.
CSE378 Instr. encoding.1 Instruction encoding The ISA defines –The format of an instruction (syntax) –The meaning of the instruction (semantics) Format.
Registers and MAL Lecture 12. The MAL Architecture MAL is a load/store architecture. MAL supports only those addressing modes supported by the MIPS RISC.
1 Compilers Modern Compiler Design Supplementary Note 2 SPIM Overview NCYU C. H. Wang.
CSCI 136 Lab 1: 135 Review.
1 Computer Architecture COSC 3430 Lecture 3: Instructions.
Ch2b- 2 EE/CS/CPE Computer Organization  Seattle Pacific University Thanks for all the Memory! When 32 registers just won’t do. Many times (almost.
Computer Organization and Architecture Instructions: Language of the Machine Hennessy Patterson 2/E chapter 3. Notes are available with photocopier 24.
CWRU EECS 3221 Language of the Machine EECS 322 Computer Architecture Instructor: Francis G. Wolff Case Western Reserve University.
Chapter 2 — Instructions: Language of the Computer — 1 Memory Operands Main memory used for composite data – Arrays, structures, dynamic data To apply.
Chapter 2 — Instructions: Language of the Computer — 1 Conditional Operations Branch to a labeled instruction if a condition is true – Otherwise, continue.
DR. SIMING LIU SPRING 2016 COMPUTER SCIENCE AND ENGINEERING UNIVERSITY OF NEVADA, RENO Session 7, 8 Instruction Set Architecture.
MIPS assembly syntax Home Assignment 3 Assigned. Deadline 2016 February 14, Sunday.
Computer Organization Instructions Language of The Computer (MIPS) 2.
CS 312 Computer Architecture & Organization
Computer Architecture & Operations I
Computer Architecture & Operations I
System Calls & Arithmetic
MIPS Instruction Set Advantages
Morgan Kaufmann Publishers
ITEC113 Algorithms and Programming Techniques
RISC Concepts, MIPS ISA Logic Design Tutorial 8.
CSCI206 - Computer Organization & Programming
MIPS coding.
Instructions - Type and Format
Week 5 Computers are like Old Testament gods; lots of rules and no mercy. Joseph Campbell.
MPIS Instructions Functionalities of instructions Instruction format
Systems Architecture I (CS ) Lecture 5: MIPS Instruction Set*
CSCI206 - Computer Organization & Programming
The University of Adelaide, School of Computer Science
MIPS History MIPS is a computer family
MIPS History MIPS is a computer family
Computer Instructions
Computer Architecture
Instruction encoding The ISA defines Format = Encoding
COMS 361 Computer Organization
UCSD ECE 111 Prof. Farinaz Koushanfar Fall 2018
Instruction encoding The ISA defines Format = Encoding
COMS 361 Computer Organization
Instruction encoding The ISA defines Format = Encoding
MIPS History MIPS is a computer family
MIPS coding.
Generalities for Assembly Language
MIPS Assembly Language Programming Computer Architecture
Systems Architecture I (CS ) Lecture 5: MIPS Instruction Set*
MIPS Arithmetic and Logic Instructions
CS 286 Computer Architecture & Organization
Week 5 Computers are like Old Testament gods; lots of rules and no mercy. Joseph Campbell.
Presentation transcript:

Comp Sci vars & expns 1 Ch. 4 Variables and Expressions

Comp Sci vars & expns 2 Supporting high-level languages How do we use MIPS assembly language to implement – Variable declaration & initialization? – Assignment statements? – Expression evaluation?

Comp Sci vars & expns 3 Program structure ## ## File: foo.a ## ## Brief explanation of program's purpose ## ## Author: Your name ## Date: 10 February 2010 ## ####################################### # Text segment # #######################################.text.globl __start __start: [program instructions...] li $v0, 10#exit syscall ######################################## # Data segment # ########################################.data [data definitions...] ## end of file foo.a [blank line] Note: file extension.a

syscalls ServiceCall codeArgumentsResult Print_integer1$a0 = integer Print_float2$f12 = float Print_double3$f12, $f13 = double Print_string4$a0 = address of string Read_int5$v0 (integer) Read_float6$f0 (float) Read_double7$f0, $f1 (double) Read_string8$a0 = buffer, $a1 = length Exit10 Print_char11$a0 = char Read_char12$v0 (char) Comp Sci vars & expns 4

5 Variable declaration Use assembler directives – Not machine instructions – Reserve memory – Define symbols Affect data segment of memory

Comp Sci vars & expns 6 Variable declaration High-level int x; MIPS assembly x:.space 4 Symbol name Data type Reserve memory No. of bytes

Comp Sci vars & expns 7 Sequence of declarations Problem!!! char x; int y; char z;.data x:.space 1 y:.space 4 z:.space 1 0x x 0x y 0x z

Comp Sci vars & expns 8 Alignment Integer variables must be “word-aligned” Use the.align directive Syntax:.align n Semantics: assembler aligns the next reserved location on an address divisible by 2 n

Comp Sci vars & expns 9 Example.data x:.space 1.align 2 y:.space 4 z:.space 1 0x x 0x y 0x z

Comp Sci vars & expns 10 Initialization int x = 5;x:.word 5 initial value symbol name size

Comp Sci vars & expns 11.word n Reserves & initializes a word of memory n can be – Unsigned number – Signed number – Hexadecimal number Automatically aligns to word boundary – Unnecessary to use.align directive before.word

Comp Sci vars & expns 12 Byte order We will use SPIM – MIPS simulator software – Runs on many different platforms Byte order in SPIM depends on native byte order of platform Intel: little-endian PowerPC (Mac): big-endian

Comp Sci vars & expns 13 Example x:.word 5 05x 00 x 05 Little Endian

Comp Sci vars & expns 14 What about character data? char x = 'a'; x:.byte 'a'

Comp Sci vars & expns 15.byte n Reserves & initializes a byte of memory n can be – Unsigned number – Signed number – Hexadecimal number – Character in single quotes  ASCII code

Comp Sci vars & expns 16 Strings char s[] = "hello"; s:.asciiz "hello" Cstring variable Array of char (Null-terminated)

Comp Sci vars & expns 17.asciiz s S is a string in double quotes Sequence of bytes is reserved & initialized One byte per character Final byte contains null character: 0x00 Note: not affected by byte order. – Leftmost char  lowest address – Rightmost char  highest address

Comp Sci vars & expns 18 Example x:.asciiz "hello" 0x68x 0x65 0x6c 0x6f 0x00 See Chapter03/data.a

Comp Sci vars & expns 19 Assignment Store a value in a variable Occurs at runtime, not compile/assemble time Supported with assembly language instructions

Comp Sci vars & expns 20 Simple assignment int x; x = 5;.text li $t0, 5 #load immediate sw $t0, x #store word.data x:.space 4

Comp Sci vars & expns 21 Load immediate instruction li reg, value value is loaded into register Value is part of the instruction – not contained in data segment – not contained in register

Comp Sci vars & expns 22 Store word instruction sw reg, address register contents are copied into memory address can be a symbol or a number address must be word-aligned – otherwise exception is raised

Comp Sci vars & expns 23 Load/Store architecture MIPS is a Reduced Instruction Set Computer (RISC) Philosophy: superior performance through – simple instructions – small instruction set – fast instructions Some operations require several instructions – assignment requires load & store

Comp Sci vars & expns 24 Assignment of char data char y; y = 'a';.text li $t0, 'a' #MSBs of $t0=0 sb $t0, y #store byte.data y:.space 1

Comp Sci vars & expns 25 Store byte instruction sb reg, address low-order byte of register is copied into memory

Comp Sci vars & expns 26 Assignment between variables int x; int y = 5; x = y;.text lw $t0, y sw $t0, x #store word.data x:.space 4 y:.word 5

Comp Sci vars & expns 27 Load word instruction lw reg, address word of memory is copied into register address must be word-aligned Note: memory  memory transfer requires two instructions

Comp Sci vars & expns 28 Assignment between char variables char a; char b = a = b;.text lbu $t0, b1 #load byte #unsigned sb $t0, a.data a:.space 1 b1:.byte #b assembly # error

Comp Sci vars & expns 29 Load byte unsigned instruction lbu reg, address byte of memory is copied into LSB of register MSBs are cleared (= 0)

Comp Sci vars & expns 30 Exercise Write equivalent MIPS code Sketch memory layout int x = 25; char a = '*'; int y; char b; y = x; b = a;

Comp Sci vars & expns 31 Arithmetic expressions High level language feature How do we evaluate expressions in assembly language? – Single operator – Multiple operators

Comp Sci vars & expns 32 Addition Expression MIPS code li $t1, 2 li $t2, 3 add $t0, $t1, $t2 Goal: result in $t0

Comp Sci vars & expns 33 Add instruction add rd, rs, rt All operands must be registers First operand is destination Second and third operands are sources rd  rs + rt Register may appear as source and destination Signed overflow  exception is raised

Comp Sci vars & expns 34 Maximize register re-use Expression MIPS code li $t0, 2 li $t1, 3 add $t0, $t0, $t1 Goal: result in $t0

Comp Sci vars & expns 35 Subtraction Expression MIPS code li $t0, 2 li $t1, 3 sub $t0, $t0, $t1

Comp Sci vars & expns 36 Sub instruction sub rd, rs, rt All operands must be registers rd  rs - rt Signed overflow  exception is raised

Comp Sci vars & expns 37 Multiplication Expression 2 * 3 MIPS code li $t0, 2 li $t1, 3 mul $t0, $t0, $t1

Comp Sci vars & expns 38 Mul instruction mul rd, rs, rt (pseudo instruction) Signed multiplication All operands must be registers rd  rs * rt No exception is raised on overflow. Why? Equivalent to mult rs, rt mflo rd

Comp Sci vars & expns 39 Division Expression 2 / 3 MIPS code li $t0, 2 li $t1, 3 div $t0, $t0, $t1

Comp Sci vars & expns 40 Div instruction div rd, rs, rt Signed division All operands must be registers rd  rs / rt Signed overflow  exception is raised

Comp Sci vars & expns 41 Remainder (% operator) Expression 2 % 3 MIPS code li $t0, 2 li $t1, 3 rem $t0, $t0, $t1

Comp Sci vars & expns 42 Rem instruction rem rd, rs, rt For simplicity, stick to non-negative operands All operands must be registers rd  rs % rt

Comp Sci vars & expns 43 Multi-operator expressions (1 + 2) * (3 – 4) Order of operations depends on – Precedence rules – Associativity – Parentheses Several orders are possible + - * - + *

Comp Sci vars & expns 44 Left-to-right evaluation method Read expression left to right Constant or variable  lowest unused t-reg Operator – Wait until both operands in registers – Perform operation – Result  left operand register

Comp Sci vars & expns 45 Exercise Apply left-to-right method to (1 + 2) * (3 – 4)

Comp Sci vars & expns 46 Optimization Sometimes you can do better than l-t-r – Fewer registers – Fewer instructions Advanced topics – Sethi-Ullman numbering (minimize registers) – Common subexpressions (minimize instructions)

Comp Sci vars & expns 47 Optimization exercise x + y * z – y L-t-r evaluation code Minimize number of registers Minimize number of instructions