Unit IV Self-Test and Test Algorithms

Syllabus Built-In self Test – test pattern generation for BIST – Circular BIST – BIST Architectures –Testable Memory Design – Test Algorithms – Test generation for Embedded RAMs.

What is BIST? On circuit Random pattern generation, very long tests Test pattern generation Response verification Random pattern generation, very long tests Response compression IC

WHAT IS BIST ? (contd.) BIST (Built-In Self-Test) : is a design technique in which parts of a circuit are used to test the circuit itself . Hardcore : Parts of a circuit that must be operational to execute a self test BIST categories : Memory BIST Logic BIST Logic + Embedded memory (ASICs) Applications : Mission-critical sytems, self-diagnostic circuitry (consumer electronics).

SoC BIST Optimization: - testing time  - memory cost  System on Chip Core 2 Core 3 Core 4 Core 5 Embedded Tester Core 1 Test access mechanism BIST Test Controller Tester Memory Optimization: - testing time  - memory cost  - power consumption  - hardware cost  - test quality 

Built-In Self-Test (BIST) Motivations for BIST: Need for a cost-efficient testing (general motivation) Doubts about the stuck-at fault model Increasing difficulties with TPG (Test Pattern Generation) Growing volume of test pattern data Cost of ATE (Automatic Test Equipment) Test application time Gap between tester and UUT (Unit Under Test) speeds Drawbacks of BIST: Additional pins and silicon area needed Decreased reliability due to increased silicon area Performance impact due to additional circuitry Additional design time and cost

BIST in Maintenance and Repair Useful for field test and diagnosis (less expensive than a local automatic test equipment) Disadvantages of software tests for field test and diagnosis (nonBIST): Low hardware fault coverage Low diagnostic resolution Slow to operate Hardware BIST benefits: Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis

BIST Techniques BIST techniques are classified: on-line BIST - includes concurrent and nonconcurrent techniques off-line BIST - includes functional and structural approaches

On-line BIST On-line BIST - testing occurs during normal functional operation Concurrent on-line BIST - testing occurs simultaneously with normal operation mode, usually coding techniques or duplication and comparison are used Nonconcurrent on-line BIST - testing is carried out while a system is in an idle state, often by executing diagnostic software or firmware routines

Off-line BIST Off-line BIST - system is not in its normal working mode, usually on-chip test generators and output response analyzers or microdiagnostic routines Functional off-line BIST is based on a functional description of the Component Under Test (CUT) and uses functional high-level fault models Structural off-line BIST is based on the structure of the CUT and uses structural fault models (e.g. SAF)

BIST key elements Circuit under test (CUT) Test pattern generators (TPG) Output response analyzer (ORA) Distribution system for data transmission between TPG, CUT and ORA BIST controller

General Architecture of BIST BIST components: Test pattern generator (TPG) Test response analyzer (TRA) TPG & TRA are usually implemented as linear feedback shift registers (LFSR) Two widespread schemes: test-per-scan test-per-clock

BIST architecture Chip, Board or System CUT ORA BIST controller TPG

Detailed BIST Architecture

Test Pattern Generation Techniques Exhaustive : Applying all 2**n input combinations, generated by binary counters or complete LFSR. Pseudoexhaustive : Circuit is segmented & each segment is tested exhaustively(Less no. of tests required): Logical segmentation : Cone + Sensitized-path Physical segmentation

Pseudoexhaustive Testing Pseudo-exhaustive test sets: Output function verification maximal parallel testability partial parallel testability Segment function verification Output function verification 4 Primitive polynomials Segment function verification F & 1111 0101 0011 216 = 65536 Pseudo- exhaustive sequential >> 4x16 = 64 Pseudo- exhaustive parallel > 16 Exhaustive test

Test Pattern Generation Techniques (Contd.) Pseudorandom : Not all 2**n input combinations, Random patterns generated deterministically & repeatably, pattern with/without replacement, applicable to both combinational and sequential circuits. weighted : Non-uniform distribution of 0’s & 1’s, improved fault coverage, using LFSR added with combinational circuits. Adaptive : Using intermediate results of fault simulation to modify 0’s & 1’s weights, more efficient,more hard ware complexity.

Built-In Self-Test Test per Scan: Initial test set: T1: 1100 T2: 1010 Test application: 1100 T 1010 T 0101T 1001 T Number of clocks = (4 x 4) + 4 = 20 Assumes existing scan architecture Drawback: Long test application time

Built-In Self-Test Test per Clock: Combinational Circuit Under Test T1 Initial test set: T1: 1100 T2: 1010 T3: 0101 T4: 1001 Test application: 1 10 0 1 0 1 0 01 01 1001 Number of clocks = 8 < 20 Combinational Circuit Under Test T1 Scan-Path Register T4 T3 T2

Pattern Generation Store in ROM – too expensive Exhaustive – too long Pseudo-exhaustive Pseudo-random (LFSR) – Preferred method Binary counters – use more hardware than LFSR Modified counters Test pattern augmentation ( Hybrid BIST) LFSR combined with a few patterns in ROM

LFSR Based Testing: Some Definitions Exhaustive testing – Apply all possible 2n patterns to a circuit with n inputs Pseudo-exhaustive testing – Break circuit into small, overlapping blocks and test each exhaustively Pseudo-random testing – Algorithmic pattern generator that produces a subset of all possible tests with most of the properties of randomly-generated patterns LFSR – Linear feedback shift register, hardware that generates pseudo-random pattern sequence BILBO – Built-in logic block observer, extra hardware added to flip-flops so they can be reconfigured as an LFSR pattern generator or response compacter, a scan chain, or as flip-flops

Pattern Generation Pseudorandom test generation by LFSR: Using special LFSR registers Test pattern generator Signature analyzer Several proposals: BILBO CSTP Main characteristics of LFSR: polynomial initial state test length

Pseudorandom Test Generation LFSR – Linear Feedback Shift Register: Standard LFSR x x2 x3 x4 x3 x2 x4 x Modular LFSR Polynomial: P(x) = x4 + x3 + 1

Specific BIST Architecture A Centralized and Separate Board-Level BIST Architecture (CSBL) Built-In Evaluation and Self-Test (BEST) Random-Test Socket (RTS) LSSD On-Chip Self-Test (LOCST) Self-Testing Using MISR and Parallel SRSG (STUMPS) A Concurrent BIST Architecture (CBIST) A Centralized and Embedded BIST Architecture with Boundary Scan (CEBS) Random Test Data (RTD) Simultaneous Self-Test (SST) Cyclic Analysis Testing System (CATS) Circular Self-Test Path (CSTP) Built-In Logic-Block Observation (BILBO)

A Centralized and Separate Board-Level BIST Architecture (CSBL)

Built-In Evaluation and Self-Test (BEST)

Random-Test Socket (RTS)

LSSD On-Chip Self-Test (LOCST)

Self-Testing Using MISR and Parallel SRSG (STUMPS)

A Concurrent BIST Architecture (CBIST)

A Centralized and Embedded BIST Architecture with Boundary Scan (CEBS)

Random Test Data (RTD)

Simultaneous Self-Test (SST)

Cyclic Analysis Testing System (CATS)

Circular Self-Test Path (CSTP)

Built-In Logic-Block Observation (BILBO) Combined functionality of D flip-flop, pattern generator, response compacter and scan chain ELEN 468 Lecture 25

BILBO Serial Scan Mode B1 B2 = “00” Dark lines show enabled data paths ELEN 468 Lecture 25

BILBO LFSR Pattern Generator Mode B1 B2 = “01” ELEN 468 Lecture 25

BILBO in D-FF (Normal) Mode B1 B2 = “10” ELEN 468 Lecture 25

BILBO in Response Compactor Mode B1 B2 = “11” ELEN 468 Lecture 25

Importance of memories Memories dominate chip area (94% of chip area in 2014) Memories are most defect sensitive parts Because they are fabricated with minimal feature widths Memories have a large impact on total chip DPM level Therefore high quality tests required (Self) Repair becoming standard for larger memories (> 1 Mbit) % of chip area year

Memory chip cost over time Price of high-volume parts is constant in time; except for inflation Note: Slope of line matches inflation! Dollars per DRAM chip

March tests: Concept and notation A march test consists of a sequence of march elements A march element consists of a sequence of operations applied to every cell, in either one of two address orders: 1. Increasing () address order; from cell 0 to cell n-1 2. Decreasing () address order; from cell n-1 to cell 0 Note: The  address order may be any sequence of addresses (e.g., 5,2,0,1,3,4,6,7), provided that the  address order is the exact reverse sequence (i.e, 7,6,4,3,1,0,2,5) Example: MATS+ {(w0);(r0,w1);(r1,w0)} Test consists of 3 march elements: M0, M1 and M2 The address order of M0 is irrelevant (Denoted by symbol ) M0: (w0) means ‘for i = 0 to n-1 do A[i]:=0’ M1: (r0,w1) means ‘for i = 0 to n-1 do {read A[i]; A[i]:=1}’ M2: (r1,w0) means ‘for i = n-1 to 0 do {read A[i]; A[i]:=0}’

Traditional tests Traditional tests are older tests Usually developed without explicitly using fault models Usually they also have a relatively long test time Some have special properties in terms of: detecting dynamic faults locating (rather than only detecting) faults Many traditional tests exist: 1. Zero-One (Usually referred to as Scan Test or MSCAN) 2. Checkerboard 3. GALPAT and Walking 1/0 4. Sliding Diagonal 5. Butterfly 6. Many, many others

Zero-One test (Scan test, (M)SCAN) Minimal test, consisting of writing & reading 0s and 1s Step 1: write 0 in all cells Step 2: read all cells Step 3: write 1 in all cells Step 4: read all cells March notation for Scan test: {(w0);(r0);(w1);(r1)} Test length: 4*n operations; which is O(n) Fault detection capability: AFs not detected Condition AF not satisfied: 1. (rx,…,wx*) 2. (rx*,…,wx) If address decoder maps all addresses to a single cell, then it can only be guaranteed that one cell is fault free Special property: Stresses read/write & precharge circuits when Fast X addressing is used and sequence of write/read 0101.... data in a column! Fast X addressing Row 000000 stripe 111111 000000 111111 Checker 010101 board 101010 010101 101010 Columns Rows

Checkerboard Is SCAN test, using checkerboard data background pattern Step 1: w1 in all cells-W w0 in all cells-B Step 2: read all cells Step 3: w0 in all cells-W w1 in all cells-B Step 4: read all cells Test length: 4*2N operations; which is O(n) Fault detection capability: Condition AF not satisfied : 1. (rx,…,wx*); 2. (rx*,…,wx) If address decoder maps all cells-W to one cell, and all cells-B to another cell, then only 2 cells guaranteed fault free Special property: Maximizes leakage between physically adjacent cells. Used for DRAM retention test!! B W 1 Step1 pattern Checkerboard data background

GALPAT and Walking 1/0 GALPAT and Walking 1/0 are similar algorithms They walk a base-cell through the memory After each step of the base-cell, the contents of all other cells is verified, followed by verification of the base-cell Difference between GALPAT and Walking 1/0 is when, and how often, the base-cell is read 0 0 0 0 0 1 0 0 Walking 1/0 0 0 0 0 0 1 0 0 GALPAT Base cell Base cell