The Verification of UniCore-II Microprocessor Sun Hanxin Peking University Microprocessor R&D Center

ICSoC2005, Aug 05 Outline Introduction to UniCore-II microprocessor Simulation-based verification methodology Bug driven activity Conclusions and future work

ICSoC2005, Aug 05 Pkunity-3 Architecture

ICSoC2005, Aug 05 UniCore-II Microprocessor UniCore Frequency: 600MHz 32-bit harvard-architecture RISC CPU UniCore32 instruction set compatible Add conditional mov & BLX instructions 8-stage instruction pipeline Dynamic prediction policy: G-share Pipelined I&D Cache Two-level TLB

ICSoC2005, Aug 05 Design Verification Problem Functional verification is widely recognized as the bottleneck of hardware design cycle:  The ever-growing demand for processor performance  The dramatically increase in hardware complexity  Low tolerance for bugs on finished product  Time-to-market pressure

ICSoC2005, Aug 05 Solution to Verification Problem Different Tests, Different Methods:  Formal Verification: Small block test  Simulation: Directed test Constrained-random test  Simulation Acceleration: Regression test  FPGA Prototyping: BIOS, Linux kernel, Application test

ICSoC2005, Aug 05 Simulation-based Verification Simulation metric Checking scheme Test generation

ICSoC2005, Aug 05 Simulation Metric Code coverage:  line coverage  toggle coverage  FSM coverage  condition coverage Functional coverage:  pipelined instruction state coverage  AHB bus transaction coverage Assertion coverage

ICSoC2005, Aug 05 Checking Scheme Self-check assembly code OpenVera assertion Golden reference model comparison

ICSoC2005, Aug 05 Checking Scheme SystemC in the design flow:  Find out problems of documented specification  Evaluate design early in the design cycle  Golden reference model of RTL design verification

ICSoC2005, Aug 05 Test Program Generation The key issue of processor verification:  Test vector efficiency  Verification time  Quality of product Some examples of processor verification:  Intel Pentium-4 verification  Alpha21164 verification  IBM Genesys, GenesysPro test generator

ICSoC2005, Aug 05 Test Program Generation UniGener: UniCore-II test program generator

ICSoC2005, Aug 05 Bug Driven Activity UniCore-II Bug trends: Bug driven activity of UniCore-II processor verification:

ICSoC2005, Aug 05 Bug Analysis: Example Bug 原因 发现方式 总计 占 Bug 总 量 百分比 代码 检查 定向 测试 定向 比对 随机 比对 随机 断言 FPGA 笔误 对设计规范理解错误 对接口规范理解不一致或不清晰 设计结构错误 对设计内部细节考虑不全面 已有设计发生逻辑错误 总计

ICSoC2005, Aug 05 Conclusions Different tests, different methods. Metric-checking-generation triangle Processor verification needs an efficient test program generator UniCore-II test program generator: UniGener Bug driven activity

ICSoC2005, Aug 05 Future Work Introduce more useful concept on coverage of processor verification Introduce more algorithm to UniGener We’re glad to discuss with you about UniGener

ICSoC2005, Aug 05 Thank you