Copyright © 2002 Qualis Design Corporation Industry and Textbook Overview Qualis Design Corporation PO Box 4444 Beaverton, Oregon USA Phone: FAX:
Copyright © 2002 Qualis Design Corporation Verification Process Involves Methods Tools People
Copyright © 2002 Qualis Design Corporation Verification in Design Flow Architectural System Design Component Specifications Synthesis & Layout RTL Design & Coding C/C++ Paper Verilog, VHDL Simulation Proofs Simulation Proofs Physical Synthesis Physical Synthesis
Copyright © 2002 Qualis Design Corporation Verification vs Testing SpecHDL Design Testbench Synthesis Equivalence Checking Manufacture DFT GatesSilicon Testing Functional Verification Functional Verification
Copyright © 2002 Qualis Design Corporation People in Verification "We do not have the resources to have dedicated verification engineers" –Amount of work is the same –Slice it differently Design & Verification Design Verification
Copyright © 2002 Qualis Design Corporation People in Verification "I'm the best hardware designer. Therefore I know how to write testbenches" –Verification and design have different focus Design: meeting performance requirements –Optimism –Coding & design style –Implementation architecture Verification: make sure intent has been implemented –Paranoia –Requirement traceability –Controllability & observability
Copyright © 2002 Qualis Design Corporation People in Verification "I'm the best hardware designer. Therefore I know how to write testbenches" –Testbench design requires different skills from hardware design Design: timing closure –Scripting –Physical effects –Power, timing Verification: software engineering –Configuration management –Abstraction & Objected oriented –Random generation & coverage
Copyright © 2002 Qualis Design Corporation People in Verification "I want to be a hardware designer when I grow up" –Hardware design has all the glory Spread to verification effort –Properly-designed verification environments require more creativity than design –More freedom in verification No subset No performance constraints No technology constraints –All cool, new tools are in verification –Develop verification training & career paths
Copyright © 2002 Qualis Design Corporation People in Verification Supply industry aligning with task separation –P&L business units –Separate sales force –Specialized consultants and AEs –Verification-only companies EDA Services IP –Verification curriculum in universities
Copyright © 2002 Qualis Design Corporation Manual Checking Unfortunately, very common Use waveform viewer to interpret results Non reproducible Sensitive to misinterpretations Cannot handle large number of transactions Stimulus DUT Vector file Simulator Viewer
Copyright © 2002 Qualis Design Corporation Golden Vectors Natural extension of DFT & visual check Compare results against known good results Stimulus Vector file Simulator Viewer Vector file Comparator DUT
Copyright © 2002 Qualis Design Corporation Compute expected results on-the-fly Significant effort investment Tolerant of non-functional variations Typical for datacom On-The-Fly Self-Checking BFM (Compare) Stimulus DUT Scoreboard Transfer function Data Structure
Copyright © 2002 Qualis Design Corporation Response verified against reference model Compare function must tolerate non-functional differences Typical for DSP and CPU –C reference model part of spec Post-Processing Self-Checking File Simulator File Comparator Stimulus DUT REF Other
Copyright © 2002 Qualis Design Corporation Traditional Approach Self-checking not a requirement Used with HDLs, or C/C++ Large number of testbenches Progress measured against check-list Time % Testcases Goal Stimulus
Copyright © 2002 Qualis Design Corporation Random Approach Progress measured using functional coverage metrics Time % Testcases Goal Self-checking, random test environment development time Self-checking, random test environment development time Stimulus
Copyright © 2002 Qualis Design Corporation Random Vs Traditional Time % Testcases Goal Productivity gain Productivity gain
Copyright © 2002 Qualis Design Corporation Formal vs Random Vs Traditional Time % Testcases Goal Productivity gain Productivity gain Formal Verification (Assertions) Formal Verification (Assertions)
Copyright © 2002 Qualis Design Corporation PPP Packet Scoreboard PPP Gen PPP Mon Testcases PPP Gen PPP Mon PPP Gen PPP Mon HDLC Ethernet SPI4.2 CSIX Network Processor Verification IP
Copyright © 2002 Qualis Design Corporation PPP Packet Scoreboard PPP Gen PPP Mon Testcases PPP Gen PPP Mon PPP Gen PPP Mon HDLC Ethernet SPI4.2 CSIX Network Processor Verification IP
Copyright © 2002 Qualis Design Corporation Time % Testcases Goal Productivity gain Productivity gain Verification IP Verification IP helps reduce time-to-first-test Earlier time-to-1st-test
Copyright © 2002 Qualis Design Corporation Industry Status Pop. Size LaggardsLeaders Self-Checking Ad-Hoc Specman, Vera Specman, Vera Specs Coverage Driven Coverage Driven Formal Verification Formal Verification Transactions Verification Plan Verification Plan Verification Engineers Custom Environment
Copyright © 2002 Qualis Design Corporation My Book Pop. Size LaggardsLeaders Self-Checking Ad-Hoc Specman, Vera Specman, Vera Specs Coverage Driven Coverage Driven Formal Verification Formal Verification Transactions Verification Plan Verification Plan Verification Engineers Custom Environment
Copyright © 2002 Qualis Design Corporation My Book
Copyright © 2002 Qualis Design Corporation Genesis of the Book Self-checking transaction-level testbenches based on verification plan and behavioral model –Nortel Networks, 1992 Consulting services in verification –Self-employed, 1994 Advanced verification class (3 days) –Qualis Design, 1996 Book started –Dining room table, 1999
Copyright © 2002 Qualis Design Corporation Objectives of the Book Functional verification is critical There is a process to functional verification Functional verification is different from design Engineers don't know HDLs as well as they think they do Improve software engineering skills
Copyright © 2002 Qualis Design Corporation For Undergrad Class Chapter 1: What is Verification? –Why should you care Chapter 2: Verification Tools –What should you use Chapter 3: Verification Plan –What should you do Chapter 4: Non-RTL Coding –There is (better) life beyond RTL –Verilog is not that easy to learn well
Copyright © 2002 Qualis Design Corporation For Undergrad Class Chapter 5: Stimulus and Response –How should you stimulate –How should you observe –How do you know it's correct Appendix A: Coding Guidelines –How you should write your code
Copyright © 2002 Qualis Design Corporation For Graduate Class Chapter 3: Verification Plan –What should you do Chapter 4: Non-RTL Coding –There is (better) life beyond RTL –Verilog is not that easy to learn well Chapter 6: Architecting Testbenches –How to minimize your effort –Wrestling with VHDL Chapter 7: Simulation Management –Actually using the stuff
Copyright © 2002 Qualis Design Corporation For Professional Class Chapter 3: Verification Plan –What should you do Chapter 4: Non-RTL Coding –There is (better) life beyond RTL –Verilog is not that easy to learn well Chapter 5: Stimulus and Response –How should you stimulate –How should you observe –How do you know it's correct
Copyright © 2002 Qualis Design Corporation For Professional Class Chapter 6: Architecting Testbenches –How to minimize your effort –Wrestling with VHDL Chapter 7: Simulation Management –Actually using the stuff
Copyright © 2002 Qualis Design Corporation For Prelude to HVLs Chapter 1: What is Verification? –Why should you care Chapter 2: Verification Tools –What should you use Chapter 3: Verification Plan –What should you do Chapter 5: Stimulus and Response –How should you stimulate –How should you observe –How do you know it's correct
Copyright © 2002 Qualis Design Corporation In Future Edition Chapter 2: Verification Tools –Assertions –Formal verification tools –HVLs (Specman, VERA) –Functional Coverage Chapter 3: Verification Plan –Coverage-driven plan Chapter 4: Non-RTL Coding –HVLs
Copyright © 2002 Qualis Design Corporation In Future Edition Chapter 5: Stimulus and Response –Scoreboarding Chapter 6: Architecting Testbenches –Constrainable Random Generation –Functional Coverage Chapter 7: Simulation Management –HVLS as reference models –Seed management
Copyright © 2002 Qualis Design Corporation Support Material Quiz – –3 questions per chapters –Answers supplied Verification Project – –4-port ATM switch –Design specification –Behavioral model (Verilog, VHDL) –Partial solutions provided by contributors
Copyright © 2002 Qualis Design Corporation Notes
Notes
Industry and Textbook Overview Qualis Design Corporation PO Box 4444 Beaverton, Oregon USA Phone: FAX: