Rapid prototyping platforms. Giving you the freedom to design solutions Providing Adopting Technology Adopting Technology to Process the Future.

Slides:



Advertisements
Similar presentations
By Sunil G. Kulkarni, SO/F, Pelletron-Linac Facility, BARC-TIFR. 21/01/2011 ASET.
Advertisements

Flexible I/O in a Rigid World
Sundanc e High-tech DSP solutions. Giving you the freedom to design Multiprocessor Technology Ltd SOFTWARE UTILITY TOOLS.
© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
StreamBlade SOE TM Initial StreamBlade TM Stream Offload Engine (SOE) Single Board Computer SOE-4-PCI Rev 1.2.
Sundance Multiprocessor Technology SMT702 + SMT712.
Connect Tech Introduction January 2013 January 2013.
Integrated Tests of a High Speed VXS Switch Card and 250 MSPS Flash ADC Hai Dong, Chris Cuevas, Doug Curry, Ed Jastrzembski, Fernando Barbosa, Jeff Wilson,
ESODAC Study for a new ESO Detector Array Controller.
Challenges in Hybrid DSP/FPGA Implementations of Optimal Beamforming
Offering the freedom to design solutions Sundance PXIe Solution.
Parallel JPEG2000 Compression System Performed by: Dmitry Sezganov, Vitaly Spector Instructor: Stas Lapchev, Artyom Borzin.
Software Defined Radio
Yifat Manzor Reshef Dahan Instructor: Eran Segev Characterization presentation December 2003.
Configurable System-on-Chip: Xilinx EDK
Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Front Page M.Meyer June 05 NGC High.
Implementation of DSP Algorithm on SoC. Mid-Semester Presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak.
Using FPGAs with Embedded Processors for Complete Hardware and Software Systems Jonah Weber May 2, 2006.
Call Center – What Really Makes Sense? Call Center – ce este cu adevarat important?
Anne Mascarin DSP Marketing The MathWorks
General Purpose FIFO on Virtex-6 FPGA ML605 board midterm presentation
© 2011 Xilinx, Inc. All Rights Reserved Intro to System Generator This material exempt per Department of Commerce license exception TSU.
Delevopment Tools Beyond HDL
Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf
General Purpose FIFO on Virtex-6 FPGA ML605 board Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf 1 Semester: spring 2012.
Wir schaffen Wissen – heute für morgen 24 August 2015PSI,24 August 2015PSI, Paul Scherrer Institut Status WP 8.2 RF Low Level Electronic Manuel Brönnimann.
Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January
Open, Scalable Real-Time Solutions Pentium Core Solo or Duo 1.6 to 2 GHz or Single or dual-core Pentium support in hard real-time up to.
W.Skulski Phobos Workshop April /2003 Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module) Wojtek Skulski University.
© Copyright Xilinx 2004 All Rights Reserved 9 November, 2004 XUP Virtex-II Pro Development System.
NetBurner MOD 5282 Network Development Kit MCF 5282 Integrated ColdFire 32 bit Microcontoller 2 DB-9 connectors for serial I/O supports: RS-232, RS-485,
Ross Brennan On the Introduction of Reconfigurable Hardware into Computer Architecture Education Ross Brennan
FPGA based Software Defined Radio Centre de Recherche INRIA – Rennes Bretagne Atlantique Abstract Software defined radio (SDR) opens a new door to future.
Model-Based Design and SDR Fabio Ancona Sundance Italia SRL CEO – Sales Director.
Silicon Building Blocks for Blade Server Designs accelerate your Innovation.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
1 LabVIEW DSP Test Integration Toolkit. 2 Agenda LabVIEW Fundamentals Integrating LabVIEW and Code Composer Studio TM (CCS) Example Use Case Additional.
1 WORLD CLASS – through people, technology and dedication High level modem development for Radio Link INF3430/4431 H2013.
Embedded Sales Meeting New Product Update. What’s New at Acromag 1. PCIe Industry Pack Carrier 2. Update - cPCI IP Carrier 3. New IP Modules 4. PMC based.
Altera Technical Solutions Seminar Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration.
Concept of Modular Design Module Carriers Embedded or PC-Host Modules A/D,D/A,I/O DSP,FPGA IMAGING,MEMORY Systems Data Acquisition Medical Industrial Control.
Dec 8-10, 2004EPICS Collaboration Meeting – Tokai, Japan MicroIOC: A Simple Robust Platform for Integrating Devices Mark Pleško
Xilinx Programmable Logic Design Solutions Version 2.1i Designing the Industry’s First 2 Million Gate FPGA Drop-In 64 Bit / 66 MHz PCI Design.
XFEL The European X-Ray Laser Project X-Ray Free-Electron Laser Dariusz Makowski, Technical University of Łódź LLRF review, DESY, 3-4 December 2007 Advanced.
ATCA based LLRF system design review DESY Control servers for ATCA based LLRF system Piotr Pucyk - DESY, Warsaw University of Technology Jaroslaw.
FPGA (Field Programmable Gate Array): CLBs, Slices, and LUTs Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side.
SW and HW platforms for development of SDR systems SW: Model-Based Design and SDR HW: Concept of Modular Design and Solutions Fabio Ancona Sundance Italia.
Open, Scalable Real-Time Solutions Intel Core 2 Duo to Quad processor up to 5 VIRTEX II Pro FPGA board RT-LAB, SIMULINK, RTW, XILINX SG.
1 Abstract & Main Goal המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory The focus of this project was the creation of an analyzing device.
September 19-20, 2007 A.Zaltsman EBIS RF Systems RF System Overview Alex Zaltsman September 19-20, 2007 DOE Annual Review.
Acromag at a Glance Presented by Russ Nieves International Sales Manager.
Connect Tech Introduction April About Connect Tech General Introduction Connect Tech is a privately held hardware design company. For more than.
1 EDK 7.1 Tutorial -- SystemACE and EthernetMAC on Avnet Virtex II pro Development Boards Chia-Tien Dan Lo Department of Computer Science University of.
Part A Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.
Xilinx Programmable Logic Development Systems Alliance Series version 3.
CORE Generator System V3.1i
This material exempt per Department of Commerce license exception TSU Xilinx On-Chip Debug.
PSI Power Supply Controls MedAustron Controls Workshop 1 PR a-FMO-PSI_Power_Supply_Controls.pptx F. Moser - PSI Power Supply Controls 1.
Industrial Controls Engineering Department First CERN PXI Users Group meeting 19 th October 2011 – Hubert REYMOND – EN/ICE 1.
Offering the freedom to design solutions Sundance OEM Solution.
An Overview of Support of Small Embedded Systems with Some Recommendations Controls Working Group April 14, 2004 T. Meyer, D. Peterson.
ATCA based LLRF system design review DESY Control servers for ATCA based LLRF system Piotr Pucyk - DESY, Warsaw University of Technology Jaroslaw.
Programmable Hardware: Hardware or Software?
Hands On SoC FPGA Design
Current DCC Design LED Board
The Complete Solution for Cost-Effective PCI & CompactPCI Implementations 1.
MAPLD Vendor Announcement Session
A Digital Signal Prophecy The past, present and future of programmable DSP and the effects on high performance applications Continuing technology enhancements.
Xilinx Alliance Series
Presentation transcript:

Rapid prototyping platforms. Giving you the freedom to design solutions Providing Adopting Technology Adopting Technology to Process the Future

Company background World-Wide Customer Base Employee owned Established in 1989 by current Directors Specialised in Multiprocessor DSP-FPGA Systems Main office in the UK (ISO , EN compliant) Sales offices in USA, Europe and Asia Network of Distributors all over the World

Our goals To make life as simple as possible for our Customers To help our customers develop cost-effective systems To support high-performance and reliable applications by working at the leading edge of the technology

The Processing Problem….

Our products Reduce time to market Rapid prototyping Flexible Reliable Scalable

Modular COTS Carrier board Modules Systems PCI, PCIe, cPCI, PXI, VME, VXS, PMC, PrPMC, PC104, Standalone DSP, FPGA, ADC, DAC, Imaging, IO, Memory SDR, Wireless, Radar, Sonar, Telecom, Medical, Industrial control, Imaging, Simulation, Monitoring

Latest technology and tools  Diamond DSP  Diamond FPGA  Model-Based design  Simulink for DSP and FPGA  Rocket IO  Virtex-4  C6455  DM642  Handel-C for FPGA  Simulink for FPGA

Winning partnerships Leading edge Alliances to offer Optimum solutions!

World’s fastest FPGAs  Virtex-4 TIM  Ultra high-performance Signal processing  XC4VSX35  XC4VSX55  Embedded processing and Serial connectivity  XC4VFX60  High-performance logic  XC4VLX160  Virtex-II Pro TIM  XC2VP30, XC2VP70

Highest performances DSP  Quad-DSP TIM  1GHz  720MHz  Dual-DSP TIM  1GHz  300MHz  Single-DSP TIM  1GHz  1GHz  720MHz

ADC, DAC, IO, Imaging, Memory solutions  Ethernet, Internet, TCP-IP  Fiber channel interface  Serial ATA Storage  High capacity DDR memory  Framegrabber  Advanced imaging  Multiple-way video inputs  IF/RF Front End  Signal generators  …

Software Defined Radio  SMT8101  1GHz DSP  XC2VP30  8-bit ADC (1GHz)  14-bit DAC (1GHz)  SMT8096  1GHz DSP  XC2VP30  14-bit ADC (125Msps)  16-bit DAC (500Msps)

The Sundance solution

The Serial Link solution

Embedded systems  External Development Systems  Flexibility and Universal  Design, Maintenance  Custom Bespoke Systems  Hazardous environments  Custom integration  External enclosure design

Development systems  PC Development Systems  Pre-installed Software  Pre-configured Hardware  Bespoke Ruggedised Systems  Custom integration  External enclosure design  Portable solutions  Rack-mountable solutions

Accelerated development All about Sundance People, Contacts, QA info Instant Product information Hi resolution photographs, both sides of PCB Functional Diagrams, PCB layout Full Design Specification documents User manuals, Application notes, published papers… Prices Upon Request FPGA VHDL source codes, constraint files FPGA ISE synthesis projects Full schematics, MTBF figures

IP Cores and Libraries  FPGA IPs  Wideband DDC  Polyphase Filterbank  JPEG Compression  DSP Optimised libraries  Floating-point Vector ibrary  Math Functions library  Imaging Graphics processing library

Dedicated Design flows

Help system  Sundance Wizard  Software updates  Tools configuration  Hardware setup  Help files and examples  DSP support  FPGA support  ADC/DAC support

Rapid Technical Support General and FAQ Sections Latest versions of Software Troubleshooting, Debug, etc. Dedicated Forums Unique forum per Customer Password protected Dedicated Technical person Dedicated Sales person Telephone Support Call anytime to anybody Direct lines to Design Engineers No “intermediate” people All Free of Charge!

The future in your hand…. Developing World-Class Platforms for World-Class Customers!