AMCOM HYDRA 70 PROJECT Mechanical Engineers Filiz Genca Jeff Kohlhoff Jason Newquist

MK66 Rocket Motor Produces 1335 lbs of thrust Propellant burn lasts 1.2s Grooves in exhaust port create missile spin of 10 rps Wrap-around fins pop out as missile clears launcher Internal threads on front end to receive warhead

M261 Warhead Cargo warhead consisting of 9 submunitions Submunition fuzes armed by a force greater than 27g’s Discharge from warhead by expulsion charge Aft end of warhead has external threads for attachment to motor

PROJECT OBJECTIVES Mechanical Perspective Upgrade the existing missile system to an LCPK (low cost precision kill) Weapon Provide guidance mechanisms to allow the missile to correct deviations from path to target after launch Missile must remain compatible with M261 Launcher

DESIGN CONSIDERATIONS Dimensions: Weight: 34.4 lbs max Length: 79.7 inches max Outer Diameter: 2.974 inches max Center of Gravity

Problem Solution Create an avionics module that can be added in between motor and warhead Module will have built in IMU and GPS guidance systems Module will contain 4 canards actuated by servo motors that will perform flight adjustments

Existing Module Design Canards Deployed

CURRENT ACTIVITIES Contacted Project Manager from last year, Eric Alexander Obtaining full project details and data from last year Obtaining dynamic simulation software Will use two programs, DATCOM and Aerodynamic Blockset

NEXT STEP Begin familiarizing with simulation software to evaluate lasts years simulation progress Continue aerodynamic modeling Canard design Range of motion (deflection angles) Path adjustments Materials selection Create Functional Decomposition of Missile and project requirements

A word from the computer engineers… TWO processing solutions are currently under review: Altera Cyclone FPGA chipset Motorola 68K microprocessor-based implementation

Why those processing solutions? Two approaches to processing solution: General hardware solution with development of specific software (M68K) Specific hardware solution development (Altera Cyclone) with development of general software.

Motorola 68K Processor Family CISC architecture 32-bit processor 32-bit Program Counter 16-bit external data bus 16 MB linear addressing range typically 19 registers (8 data, 7 address, etc.) 16 bit ROM and RAM required for system Recognized 8 interrupt levels Multitasking system Allows for very small stacks to be used for tasks No memory allocated to hold stacks

Motorola MC68060 superscalar architecture 256 entry branch prediction cache 8 Kbytes L1 data cache 8 Kbytes L1 instruction cache 250 million operations/sec @ 50 MHz Suggested clock rate upto(?) 66MHz allows simultaneous execution of two integer instructions, one branch during each clock cycle

Altera Cyclone FPGA Chipset The Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1 ■ Up to 294,912 RAM bits (36,864 bytes) ■ Supports configuration through low-cost serial configuration device ■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ■ High-speed (640 Mbps) LVDS I/O support ■ Low-speed (311 Mbps) LVDS I/O support ■ 311-Mbps RSDS I/O support

Altera Cyclone FPGA Chipset (cont’d) ■ Up to two PLLs per device provide clock multiplication and phase shifting ■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM ■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

LabVIEW FPGA A third contender? FPGA = field-programmable gate array develop FPGA VIs (virtual instruments or programs) on a host computer running Windows, LabVIEW compiles and implements the code in hardware Timing resolution - 25 ns Loop rates ~ 40 MHz Used with National Instruments (NI) RIO (reconfigurable input/output) hardware Allows to create I/O hardware without VHDL coding or board design

LabVIEW FPGA (cont.) Group members have LabVIEW experience Strong contacts at NI Currently in contact with NI’s Nashville Field Sales Engineer regarding the potential use of manuals and hardware LabView FPGA development

We currently have: Altera Cyclone FPGA solution Licensed copy of Altera Quartus II SP2 Documentation