Threats and Challenges in FPGA Security Ted Huffmire Naval Postgraduate School December 10, 2008

Overview Foundry Trust Physical Attacks Design Tools Design Theft Problem Areas Attacks Trojan horse Backdoor Kill switch Probing Sand and Scan Side Channels Data Remanence Covert channels Side channels Bypass Cloning Reverse engineer Readback attack Solutions Trusted foundries FPGAs X-Ray Inspection Sand and Scan Tamper sensing Adding noise Degaussing Logical isolation Tracing wires Sanitization Continuous power Encrypt bitstream Watermarking Authentication Future Research All of supply chain Lessons from S/W Red teams Side channels Trusted tools Verification Languages CM High-assurance Partial reconfig PUFs High-assurance CMPs Tagging Dynamic security Reference monitor Defense in depth User training Security usability DoS Authentication Complex designs System Assurance

Reconfigurable Hardware FPGA Chip SDRAM (off-chip) DRAM Reference Monitor Crypto Core CPU Core AES μPμP μPμP

Protection Alternatives Separation Kernels DRAM app1 app3 app2 kernel Reconfigurable Protection DRAM app1 app2 app3 Reference Monitor Physical Software SpatialTemporal

Design Flows

Intertwined Cores

Moats FPGA Chip SDRAM (off-chip) DRAM Reference Monitor Crypto Core CPU Core AES

Moats 1.0

Moats 2.0

Moats and Drawbridges

Interconnect Tracing FPGA Chip SDRAM (off-chip) DRAM Reference Monitor Crypto Core CPU Core AES μPμP μPμP X X

Communication Architecture FPGA Chip SDRAM (off-chip) DRAM Arbiter/Reference Monitor Crypto Core CPU Core AES μPμP μPμP

Memory Protection FPGA Chip SDRAM (off-chip) DRAM Crypto Core CPU Core AES Reference Monitor X X

Policy Compiler

SoC Application

Questions? 