Neuroblastoma Stroma Classification on the Sony Playstation 3 Tim Hartley, Olcay Sertel, Mansoor Khan, Umit Catalyurek, Joel Saltz, Metin Gurcan Department.

Slides:



Advertisements
Similar presentations
Parallel Processing with PlayStation3 Lawrence Kalisz.
Advertisements

4. Shared Memory Parallel Architectures 4.4. Multicore Architectures
Multicore Architectures Michael Gerndt. Development of Microprocessors Transistor capacity doubles every 18 months © Intel.
Implementation of 2-D FFT on the Cell Broadband Engine Architecture William Lundgren Gedae), Kerry Barnes (Gedae), James Steed (Gedae)
Ido Tov & Matan Raveh Parallel Processing ( ) January 2014 Electrical and Computer Engineering DPT. Ben-Gurion University.
Empowering visual categorization with the GPU Present by 陳群元 我是強壯 !
Sony PLAYSTATION 3 and the Cell Processor Dr. Hayden So Department of Electrical and Electronic Engineering 3 Sep, 2008.
MSSG: A Framework for Massive-Scale Semantic Graphs Timothy D. R. Hartley, Umit Catalyurek, Fusun Ozguner, Andy Yoo, Scott Kohn, Keith Henderson Dept.
Copyright © 2006 by The McGraw-Hill Companies, Inc. All rights reserved. McGraw-Hill Technology Education Copyright © 2006 by The McGraw-Hill Companies,
ELEC 6200, Fall 07, Oct 29 McPherson: Vector Processors1 Vector Processors Ryan McPherson ELEC 6200 Fall 2007.
Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula
Fall 2008Introduction to Parallel Processing1 Introduction to Parallel Processing.
CS 7810 Lecture 24 The Cell Processor H. Peter Hofstee Proceedings of HPCA-11 February 2005.
Cell Broadband Processor Daniel Bagley Meng Tan. Agenda  General Intro  History of development  Technical overview of architecture  Detailed technical.
Madagascar on a Playstation 3 William Burnett Friday Seminar December 4, 2009.
Emotion Engine A look at the microprocessor at the center of the PlayStation2 gaming console Charles Aldrich.
Joram Benham April 2,  Introduction  Motivation  Multicore Processors  Overview, CELL  Advantages of CMPs  Throughput, Latency  Challenges.
Cell Architecture. Introduction The Cell concept was originally thought up by Sony Computer Entertainment inc. of Japan, for the PlayStation 3 The architecture.
Introduction to the Cell multiprocessor J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, D. Shippy (IBM Systems and Technology Group)
Evaluation of Multi-core Architectures for Image Processing Algorithms Masters Thesis Presentation by Trupti Patil July 22, 2009.
Parallel Home Qiong Luo Hong Kong University of Science & Technology
Cell Broadband Engine Architecture Bardia Mahjour ENCM 515 March 2007 Bardia Mahjour ENCM 515 March 2007.
Computationally Efficient Histopathological Image Analysis: Use of GPUs for Classification of Stromal Development Olcay Sertel 1,2, Antonio Ruiz 3, Umit.
Kenichi Kourai (Kyushu Institute of Technology) Takuya Nagata (Kyushu Institute of Technology) A Secure Framework for Monitoring Operating Systems Using.
Introduction CSE 410, Spring 2008 Computer Systems
National Center for Supercomputing Applications University of Illinois at Urbana-Champaign Cell processor implementation of a MILC lattice QCD application.
Introduction to CMOS VLSI Design Lecture 22: Case Study: Intel Processors David Harris Harvey Mudd College Spring 2004.
1/21 Cell Processor (Cell Broadband Engine Architecture) Mark Budensiek.
March 12, 2007 Introduction to PS3 Cell BE Programming Narate Taerat.
Programming Examples that Expose Efficiency Issues for the Cell Broadband Engine Architecture William Lundgren Gedae), Rick Pancoast.
Applying GPU and POSIX Thread Technologies in Massive Remote Sensing Image Data Processing By: Group 17 King Mongkut's Institute of Technology Ladkrabang.
SJSU SPRING 2011 PARALLEL COMPUTING Parallel Computing CS 147: Computer Architecture Instructor: Professor Sin-Min Lee Spring 2011 By: Alice Cotti.
© 2007 SET Associates Corporation SAR Processing Performance on Cell Processor and Xeon Mark Backues, SET Corporation Uttam Majumder, AFRL/RYAS.
Group May Bryan McCoy Kinit Patel Tyson Williams Advisor/Client: Zhao Zhang.
A Novel Image Registration Pipeline for 3- D Reconstruction from Microscopy Images Kun Huang, PhD; Ashish Sharma, PhD; Lee Cooper, MS; Kun Huang, PhD;
Impact of High Performance Sockets on Data Intensive Applications Pavan Balaji, Jiesheng Wu, D.K. Panda, CIS Department The Ohio State University Tahsin.
Kevin Eady Ben Plunkett Prateeksha Satyamoorthy.
Vector/Array ProcessorsCSCI 4717 – Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Vector/Array Processors Reading: Stallings, Section.
CPU Inside Maria Gabriela Yobal de Anda L#32 9B. CPU Called also the processor Performs the transformation of input into output Executes the instructions.
Group May Bryan McCoy Kinit Patel Tyson Williams.
Cell Processor Programming: An introduction Pascal Comte Brock University, Fall 2007.
Sam Sandbote CSE 8383 Advanced Computer Architecture The IBM Cell Architecture Sam Sandbote CSE 8383 Advanced Computer Architecture April 18, 2006.
Department of Computer Science MapReduce for the Cell B. E. Architecture Marc de Kruijf University of Wisconsin−Madison Advised by Professor Sankaralingam.
LYU0703 Parallel Distributed Programming on PS3 1 Huang Hiu Fung Wong Chung Hoi Supervised by Prof. Michael R. Lyu Department of Computer.
The Octoplier: A New Software Device Affecting Hardware Group 4 Austin Beam Brittany Dearien Brittany Dearien Warren Irwin Amanda Medlin Amanda Medlin.
Computer performance issues* Pipelines, Parallelism. Process and Threads.
Central Processing Unit CPU or Processor. Central Processing Unit Components Control Unit Arithmetic & Logic Unit.
Ohio State University Department of Computer Science and Engineering Servicing Range Queries on Multidimensional Datasets with Partial Replicas Li Weng,
A Look Inside The Processor
Understanding Parallel Computers Parallel Processing EE 613.
K. Sándor, M. Kozlovszky, V. Kamarás, L. Ficsór, S. V. Varga, B. Molnár HPCS 2008 April 14, 2008, Ottawa, Canada.
Presented by Jeremy S. Meredith Sadaf R. Alam Jeffrey S. Vetter Future Technologies Group Computer Science and Mathematics Division Research supported.
FFTC: Fastest Fourier Transform on the IBM Cell Broadband Engine David A. Bader, Virat Agarwal.
Porting Irregular Reductions on Heterogeneous CPU-GPU Configurations Xin Huo Vignesh T. Ravi Gagan Agrawal Department of Computer Science and Engineering,
High performance computing architecture examples Unit 2.
IBM Cell Processor Ryan Carlson, Yannick Lanner-Cusin, & Cyrus Stoller CS87: Parallel and Distributed Computing.
Servicing Seismic and Oil Reservoir Simulation Data through Grid Data Services Sivaramakrishnan Narayanan, Tahsin Kurc, Umit Catalyurek and Joel Saltz.
Introduction CSE 410, Spring 2005 Computer Systems
● Cell Broadband Engine Architecture Processor ● Ryan Layer ● Ben Kreuter ● Michelle McDaniel ● Carrie Ruppar.
Itanium® 2 Processor Architecture
High performance bioinformatics
High Performance Computing on an IBM Cell Processor --- Bioinformatics
Cell Architecture.
Assembly Language for Intel-Based Computers, 5th Edition
Low-Cost High-Performance Computing Via Consumer GPUs
Coe818 Advanced Computer Architecture
Central Processing Unit
Chapter 1 Introduction.
Multicore and GPU Programming
Multicore and GPU Programming
Presentation transcript:

Neuroblastoma Stroma Classification on the Sony Playstation 3 Tim Hartley, Olcay Sertel, Mansoor Khan, Umit Catalyurek, Joel Saltz, Metin Gurcan Department of Biomedical Informatics The Ohio State University

2 The Cell BE processor  Designed at IBM in conjunction with Toshiba and Sony (processor for the PS3)  The Cell is a 9 core chip with a shared L2 cache  One PowerPC (PPE) core  Eight Synergistic Processing Elements (SPE)  High performance I/O to support data-intensive applications

3 Cell BE parallelism  Levels of parallelism Instruction-level parallelism via 128- bit vector operations Thread-level parallelism via independent SPE processors CPU-level parallelism for extreme-scale problems  Some image analysis algorithms are appropriate to be parallelized

4 Image analysis on Cell  Neuroblastoma  Nerve cell cancer predominantly affecting children  Microscope slides can be very large (> 40 GB)  One SPE equivalent to 2.13 GHz 64-bit Intel or AMD CPU for this application

5 Details of Cell port for analysis Image label Input image LA*B* conversion L L A* B* Statistical feature extraction LBP feature Bhattacharyya distance KNN classifier Flowchart of stroma classification algorithm  Algorithm overview  Image partitioned into tiles  RGB to LAB transformation  LBP feature calculation  Computationally expensive portions  RGB to LAB transformation  LBP feature calculation  Two stages to Cell analysis pipeline  RGB->LAB and color-space statistics  LBP feature calculation

6 More details of Cell port  Instruction-level parallelism  Vector operations in pipeline stages  Thread-level parallelism  Multiple SPEs analyzing multiple tiles concurrently  Dynamic scheduling of operations on SPEs  CPU-level parallelism  Use DataCutter to decouple tile I/O from analysis  Tiles are read from storage node(s) and pushed to PS3(s)‏ `

7 Algorithm workflow Disabled (yield) Reserved Lab

8 Demo

9 Conclusion  Performance in analysis of Neuroblastoma slides  Up to 6 times faster than regular CPU with PS3  Price/performance ratio is significantly better than regular CPU  Sony and IBM encourage Linux-based development with official Software Development Kits (SDK), Linux OS installation support PlayStation is a registered trademark of Sony Computer Entertainment Inc.