Lecture # 11 University of Tehran Digital Logic Design Lecture # 11 University of Tehran

Outline Encoder Verilog

Encoder We talked about using a decoder to decode a coded number, obviously there has to also be a way of encoding data as well.

Encoder (continued…)

Encoder (continued…) As you can see in the last example of a binary encoder we have only paid attention to 5 of the 16 possible inputs, them being: I3 0 0 0 0 1 I2 0 0 0 1 0 I1 0 0 1 0 0 I0 0 1 0 0 0 Even this state has been set don’t care in our KM.

Encoder (continued…) Using the KM shown in the latter slides or simply considering the fact that y0 is active when either I1 or I3 is active and a similar observation for y1 we have:

Encoder (continued…) An encoder can find other uses as well. For instance consider a stage in a CPU’s working time when two interrupts are sent to it at the same time. One asking for the process of a key press event and the other pointing to a power failure. Obviously in such a situation the first need not be processed because the second interrupt indicates a very severe problem (specially in OSs like Linux).

Encoder (continued…) Now if in a specific problem such as what mentioned in the last slide, there does actually occur a time when two or more of the inputs are active, we will be using a priority encoder. In such a case the input line with the higher number is chosen to be of higher priority. This means that for instance if we choose X3 as a power failure interrupt line, no other interrupt request will ever surpass it through priority.

Encoder (continued…) To design this priority encoder, consider the following truth table and KMs:

Encoder (continued…)

Encoder (continued…) Note: When we use the shown encoder as an interrupt handler, GS becomes active when one of the interrupt lines become active, and the interrupt number is given to the CPU through y1y0. The GS output is in fact a path through which the interrupt handler can inform the CPU of the occurrence of an interrupt request somewhere in the system.

Encoder (continued…) Now let’s see a standard encoder package 74148 which is an 8-to-3 encoder:

Encoder (continued…) In the package 74148, the EO output (Enable Output) will be active when none of the input lines are active (simply put there to use the extra left out pin of our IC).

Encoder (continued…) The following figure shows how we can cascade two 4-to-2 encoders:

Verilog In this session we want to see how to bring our level of description higher than switch level and gate level to data flow description. Example: module MyAnd(a, b, z); input a, b; output z; assign #5 z=a&b; endmodule Other logic operators can also be used in continuous assignments such as: assign z=(a&b)|(a^b)

Verilog (continued…) The following is a code for a 4 bit adder module: module adder(a, b, z); input [3:0] a, b; output [3:0] z; assign z=a+b; endmodule

Verilog (continued…) Let’s now write a test bench for the above adder: module test_adder(); reg [3:0] aa, bb; wire [3:0] zz; adder u(aa, bb, zz); initial begin aa=4; bb=6; #10; end endmodule

Verilog (continued…) The following code shows how we can work with a part of our bus: module function(a, b, z); input [3:0] a, b; output [3:0] z; assign z=a+b; assign z[3]=a[3]^b[3]; endmodule

Verilog (continued…) Example: module adder(a, b, cin, s, cout); input [3:0] a, b; input cin; output [3:0] s; output cout; assign {cout, s}=a+b+cin; endmodule The statement {cout, s}=a+b+cin; shows concatenation of s and cout, cout being MSB and s LSB.

Verilog (continued…) Let’s take a look at some examples: A 4 bit And module: module And4bit(a, b, z); input [3:0] a, b; output [3:0] z; assign z=a&b; endmodule

Verilog (continued…) A comparator: module comparator(a, b, gt, eq, lt); input [3:0] a, b; output gt, eq, lt; assign gt=(a>b); assign lt=(a<b); assign eq=(a==b); endmodule

Verilog (continued…) 16 bit 2-to-1 multiplexer: module MUX2to1(s, a, b, z); input [15:0] a, b; input s; output [15:0] z; assign z=(s==1)?a:b; endmodule

Verilog (continued…) 4 bit 4-to-1 multiplexer: module MUX4to1(s, a, b, c, d, z); input [1:0] s; input [3:0] a, b, c, d; output [3:0] z; assign z=(s[1]==1)?((s[0]==0)?a:b):((s[0]==0)?c:d) endmodule

Verilog (continued…) Note: As we saw before we have concurrency of statements in Verilog. This concurrency is also true about assign statements, for instance the following two assign statements resemble the circuit in the figure: assign z=~a&b; assign y=z^b;