1 Bikas Das, Nikola Pekas, Rajesh Pillai, Bryan Szeto, Richard McCreery University of Alberta National Institute for Nanotechnology Edmonton, Alberta,

Slides:



Advertisements
Similar presentations
1 PIDS 7/1/01 18 July 2001 Work In Progress – Not for Publication P. Zeitzoff Contributors: J. Hutchby, P. Fang, G. Bourianoff, J. Chung, Y. Hokari, J.
Advertisements

30 nm © 2005 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice Atomic Switch ITRS Emerging.
EE 314: Basic EE II Midterm Solutions. Problem 1 What makes a material a semiconductor? What are dopants? – A semiconductor acts as an insulator at very.
Modulation of conductive property in VO 2 nano-wires through an air gap-mediated electric field Tsubasa Sasaki (Tanaka-lab) 2013/10/30.
Metal Oxide Semiconductor Field Effect Transistors
Carbon nanotube field effect transistors (CNT-FETs) have displayed exceptional electrical properties superior to the traditional MOSFET. Most of these.
Chun-Chieh Lu Carbon-based devices on flexible substrate 1.
11/29/2004EE 42 fall 2004 lecture 371 Lecture #37: Memory Last lecture: –Transmission line equations –Reflections and termination –High frequency measurements.
Future of Computation with Electronic Nanotechnogy Presented By Shubhra Karmakar.
11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.
Outline Introduction – “Is there a limit?”
Static Memory Outline –Types of Static Memory –Static RAM –Battery Backup –EPROM –Flash Memory –EEPROM Goal –Understand types of static memory –Understand.
Chapter 5 Internal Memory
Memory and Storage - Sheetal Gosrani. Overview Memory Hierarchy RAM Memory Chip Organization ROM Flash Memory.
12/1/2004EE 42 fall 2004 lecture 381 Lecture #38: Memory (2) Last lecture: –Memory Architecture –Static Ram This lecture –Dynamic Ram –E 2 memory.
Physical Memory By Gregory Marshall. MEMORY HIERARCHY.
2. Memory. Main memory – speed & types Organization of RAM RAM – Random Access Mem Static RAM [SRAM] - In SRAM, a bit of data is stored using the state.
Lecture on Electronic Memories. What Is Electronic Memory? Electronic device that stores digital information Types –Volatile v. non-volatile –Static v.
Emerging Memory Technologies
Phase change memory technology Rob Wolters September 2008.
VFET – A Transistor Structure for Amorphous semiconductors Michael Greenman, Ariel Ben-Sasson, Nir Tessler Sara and Moshe Zisapel Nano-Electronic Center,
Science and Technology of Nanostructures Physics 805, Fall 2009 F. J. Himpsel Syllabus, Info, Lecture Notes :
Device Physics – Transistor Integrated Circuit
Outlines History of Conjugated Polymers
Memristor Memory Circuits
Silicon – On - Insulator (SOI). SOI is a very attractive technology for large volume integrated circuit production and is particularly good for low –
Magnetoresistive Random Access Memory (MRAM)
National Institute of Science & Technology Technical Seminar Presentation-2004 Presented By: Arjun Sabat [EE ] Flash Memory By Arjun Sabat Roll.
Applications of Quantum Physics
Limitations of Digital Computation William Trapanese Richard Wong.
Nanotechnology for Future Generation Devices for Computation and Communication Computation (Magnetic Data Storage, CMOS Technology)‏ Communication (Interconnects)‏
Chapter 8 Memory Interface
STORAGE DEVICES Presentation By: Saurabh Mishra. A data storage device is a device for recording (storing) information (data). CD, Hard Disk and Flash.
The Memristor.
Grace Xing---EE30357 (Semiconductors II: Devices) 1 EE 30357: Semiconductors II: Devices Lecture Note #19 (02/27/09) MOS Field Effect Transistors Grace.
OCR GCSE Computing © Hodder Education 2013 Slide 1 OCR GCSE Computing Chapter 2: Memory.
1 Fundamentals of Microelectronics  CH1 Why Microelectronics?  CH2 Basic Physics of Semiconductors  CH3 Diode Circuits  CH4 Physics of Bipolar Transistors.
Nanotechnology on our Desktops Hard Disk Sensor Medium Transistor Gate SourceDrain Switching layer 5 nm Magnetic grain 10 nm Gate oxide 4 nm Well 6 nm.
1 Chapter 5. Metal Oxide Silicon Field-Effect Transistors (MOSFETs)
SPINTRONICS …… A QUANTUM LEAP PRESENTED BY: DEEPAK 126/05.
ECE 4339 L. Trombetta ECE 4339: Physical Principles of Solid State Devices Len Trombetta Summer 2007 Chapter 15: FET Introduction: The JFET and MESFET.
Introduction to Spintronics
The development of the readout ASIC for the pair-monitor with SOI technology ~irradiation test~ Yutaro Sato Tohoku Univ. 29 th Mar  Introduction.
CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES Part 2.
Memory 2. Activity 1 Research / Revise what cache memory is. 5 minutes.
31nm Al 2 O 3, ZrO 2, HfO 2, … M1 M2 M3 M4 M5 © imec 2002.
The Fate of Silicon Technology: Silicon Transistors Maria Bucukovska Scott Crawford Everett Comfort.
MEMRISTOR The Fourth Fundamental Circuit Element.
Flash Memory by Matt & Sam. What is Flash Memory? Flash memory is a type of memory storage device for computers & devices. It is a type of 'EEPROM' chip,
CS203 – Advanced Computer Architecture
MEMRISTOR A New Bond graph Element.
Norhayati Soin 06 KEEE 4426 WEEK 15/1 6/04/2006 CHAPTER 6 Semiconductor Memories.
The Devices: MOS Transistor
Nonvolatile memories:
Lecture 18 OUTLINE The MOS Capacitor (cont’d) Effect of oxide charges
Magnetoresistive Random Access Memory (MRAM)
Welcome.
Information Storage and Spintronics 10
Device Physics – Transistor Integrated Circuit
Lecture 19 OUTLINE The MOS Capacitor (cont’d) The MOSFET:
Electronics for Physicists
Paper introduction Yuna Kim
2.C Memory GCSE Computing Langley Park School for Boys.
Device Physics – Transistor Integrated Circuit
Lecture 19 OUTLINE The MOS Capacitor (cont’d) The MOSFET:
Hardware Main memory 26/04/2019.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Sung June Kim Chapter 18. NONIDEAL MOS Sung June Kim
Ionic liquid gating of VO2 with a hBN interfacial barrier
Memory Principles.
Presentation transcript:

1 Bikas Das, Nikola Pekas, Rajesh Pillai, Bryan Szeto, Richard McCreery University of Alberta National Institute for Nanotechnology Edmonton, Alberta, Canada Yiliang Wu Xerox Research Centre of Canada Redox-gated Molecular Memory Devices based on Dynamic Doping of Polythiophene

2 Today’s solid state memory (>$100 billion annually): Dynamic Random Access Memory (DRAM) Static RAM Flash (cameras, USB stick) write/erase cell retention cycle life speed size power on 1 µsec- 10 msec 1T > 10 yrs No “universal” memory- we need different types for different needs T = transistor, C = capacitor *

3 Cell Phones IEEE Nanotech Magazine, December 2009 enabled mobile electronics (cell phones, MP3 players, etc) ~$65 billion/year (not counting disk drives) 16 billion units (i.e. chips) sold in 2009 Nonvolatile solid state Memory Devices: Scifinder hits: “nonvolatile memory”: 31,800 “resistance memory”: 9,900 “conductance switching”: 10,560 “Alternative” nonvolatile memory in ITRS roadmap: Phase Change RAM Magnetic RAM Polymer memory Fuse/antifuse Molecular memory Nanomechanical

4 ethyl viologen ClO 4 + polyethylene oxide read write/erase SiO 2 S D G PQT EV polythiophene PQT from Xerox Canada S S S S C 12 H 25 H 25 C 12 n S S S S C 12 H 25 H 25 C 12 n more to scale: 1000 nm 25 nm D S initial (neutral) σ ≈ S/cm eˉ PQT + “polaron” σ ≈ 10 S/cm + - “Redox gated” molecular memory:

V SG (V) PEO Start EV(ClO 4 ) 2 +PEO I SG, µA - G S D PQT + V SG PEO or PEO/EV NHE PQT + /PQT EV +2 /EV E o’, V V SG S G V SG drives a redox reaction: PQT + EV +2 → PQT + + EV + “write” “erase”

I S-D (nA) V S-D (V) Initial read write/erase SiO 2 S D G =-2V After V SG + - I SD (0.5 V) -3 “erase” pulse … “ON” state “OFF” state +3 “write” pulse … 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E time (s) ON/OFF > 10 4 PQT EV = +2V After V SG

7 + Write - Erase 100 W/R/E/R cycles ACS Appl. Mater. Interfaces 2013, 5, Note: resistance readout low energy W/E nondestructive “read” should scale well potentially longer cycle life than “flash”

8 σ ~ 10 S/cm σ ~ S/cm PQT (neutral) Raman shift, cm -1 (vs. 780 nm) 1460 cm -1 PQT + (polaron) 1405 cm -1 Raman permits monitoring of PQT + formation in working memory device Raman spectroelectrochemistry of PQT:

σ ~ 10 S/cm σ ~ S/cm PQT PQT + Drain, initial Raman shift (cm ) Raman intensity (a.u.) Source, V SG = +2 * * Source, V SG = -2 Drain, V SG = +2 Drain, V SG = cm cm cm cm -1 S D - PQT + EV(ClO 4 ) 2 +PEO G Substrate V S-G Raman laser V SG pulses are “switching” polymer between high and low conductance states.. top view Source, initial 1460 Solid state spectroelectrochemistry:

10 V S-G S D G D S + - (a) Initial neutral Drain Source (under) Gate V SG = +2V polaron Drain Source (under) Gate G a t e V SD =-2V neutral Raman shift (cm -1 ) Drain Source (under) Gate polaron generation mediates conductance and “memory” polaron is produced in entire source/channel/drain region J. Am. Chem Soc. 2012, 134, 14869

11 S D V SG - + N P+P+ P+P+ P+P+ A¯ N N P+P+ N N N N N EV + A‾ EV +2 S D V SG 25 nm 1000 nm - + P+P+ P+P+ P+P+ P+P+ EV + A‾ A¯ N e¯ Polythiophene is not only a redox polymer but also a conducting polymer, so electron transport “laterally” is quite efficient. e¯ A¯ N N N N N N N EVA 2 S D V SG - + P+P+ P+P+ P+P+ A¯ P+P+ P+P+ P+P+ P+P+ P+P+ P+P+ EV + A‾ A‾ = ClO 4 ‾

12 Read W/E Now, monitor S-D current during +3 V S-G “write” pulse 0 V -3 V +0.5 V ~1 µm PEO-viologen PQT S D 30 nm A closer look at dynamics, using a circuit equivalent to a bi-potentiostat:

13 I SD (mA) I SD (right axis) I SG (µA) Time (s) (b) I SG (left axis) G S D Read W/E 0 V -3 V +0.5 V RC “charging” current generating conducting polaron SD conduction (“readout”) note 1000x “gain” P+P+ P+P+ P+P+ P + generation P+P+ P + propagation charging (RC) Which one(s) control speed?

14 Time (s) I SG µ(A) (a) I SG (µA) An interesting effect of atmosphere: vacuum (right scale) ACN vapor (left scale) air (right scale) I SG, “write” RC charging? ionic mobility? propagation speed? RC (msec) Ambient0.18 Vacuum0.037 ACN vapor0.081 all < 1 msec, can’t be the problem G S D R W/E 0 V -3 V +0.5 V

15 G Read W/E 0 V -3 V +0.5 V PEO-viologen S D Propagation of polarons into channel: Propagation is essential, could it be the slow step?

16 “Propagation” experiment: S D G i SG i SD i SG “write” i SD “read”, 10 µm gap propagation delay i SD “read”, 1 µm gap i SD “read”, 10 µm gap +3 V

17 Canadian ECS- 23

18 Canadian ECS- 24

19 Canadian ECS- 25

20 Canadian ECS- 26

21 Canadian ECS- 27

22 Canadian ECS- 28

23 Canadian ECS- 29

24 Canadian ECS- 30

25 PEO + ClO 4 ˉ close-up of S electrode: - +3 V + + “W” pulse generates polarons anions move toward polarons, compensate + charge polarons “fill” the Source region polarons propagate throughout PQT layer, anions continue to migrate from PEO the bad news: iR losses in PEO layer reduce “write” current, thus requiring ~ 500 msec to “fill” source region. the good news: there are solid electrolytes with conductivity >1000x higher than PEO-ClO 4, which should reduce “write” time to μsec. We can also make the electrolyte at least 10x thinner

26 Some progress: G S D drop cast PEO-EV 1-2 μm G S D spin coated PEO-EV ~0.3 μm PEO-EV Drop Cast PEO-EV Spin Coated “write” pulse PEO-EV Drop Cast PEO-EV Spin Coated “write” pulse

t, msec 26 o C 57 o C 47 o C I SG, “write” ~100 X higher “write” current than drop cast, ambient acetronitrile vapour: Note: effective “write” speed of ~2 msec instead of ~500 msec t, msec 26 o C 57 o C 47 o C I SD, “read”

28 XRCC polymer CMOS with support electronics Thin film transistor substrate Target: high “value added” to CMOS by integrating molecular nonvolatile memory

29 Low density prototype tester: