PRESENTED BY OUSSAMA SEKKAT Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios
Goal of the project To implement a revolutionary new mixed-signal baseband processor targeting the task of spectrum sensing in cognitive radios. Will use both energy detection and pilot detection
Berkeley Emulation Engine 2(BEE 2) The platform: 5 high-performance Xilinx FPGAs (Virtex II Pro 70) each containing a power PC Core Support for up to 20GB of high speed DDR2 DRAM FPGAs laid out in a star topology with four user FPGAs in a ring and one control FPGA connected to each user. User FPGAs each have four independent high speed serial channels which are capable of transferring data at 10Gbps (XAUI interface) 1 Ethernet port.
BEE 2 (Topology)
BORPH Operating System BORPH:Berkeley Os for ReProgrammable Hardware Extended Linux kernel that treats FPGA resources as native computational resources. Provides integral operating system supports for FPGA designs, such as the ability for an FPGA design to read/write to the standard Linux file system. A user process in BORPH, can therefore either be a software program running on a processor, or a hardware design running on a FPGA.
BORPH Operating System (cont.)
Cognitive radio test bed Front end board contains: FPGA board XAUI connection Baseband processor Front-end radio
Development environment MSSGE tool flow: Matlab v7.0.4 (R14) SP2 Simulink v6.2 (R14) SP2 Xilinx System Generator v7.1 Xilinx EDK v7.1.02i Xilinx ISE v7.1.04i MSSGE libraries (Simulink models etc..)
Bee2 setup SSH connection to Bee2 enabled. IP: Can use a modified RS-232 cable to connect to Bee2 as a root. Hardware process example:
Counter:
Hardware process (cont.)
matlab >> bee_xps
Hardware process (cont.)
In BEE 2: & ps PID TTY TIME CMD pts/6 00:00:00 bash pts/6 00:00:00 testborph_oussama_floating_2009_Mar_12_1523.bof pts/6 00:00:00 ps cd /proc/26488/hw ls ioreg ioreg_mode region cd ioreg ls cnt_en cnt_val cat cnt_val echo 1 >> cnt_en cat cnt_val 000AC015 cat cnt_val 000ACFF9 echo 0 >> cnt_en cat cnt_val 000ADEF3 cat cnt_val 000ADEF3
Data acquisition example Start the user FPGA process: &
Data acquisition example Start the control FPGA process: &
Data acquisition example
Initialize front end 0// Status for front end 0 --RF-- FE 0: frequency 2445 FE 0: ant_select 0 FE 0: tx_on 1 FE 0: tx_power 7 FE 0: rx_lna_gain 0 FE 0: refadj 0 FE 0: rx_agc MxFE-- FE 0: clkout1_div 0 FE 0: clkout2_div 0 FE 0: tx_dac_gain 128 FE 0: tx_pga_gain 100 FE 0: tx_two_edges 0 FE 0: tx_inv_sample 0 FE 0: tx_twos_complement 0 FE 0: tx_inv_sync 0 FE 0: tx_q_i_order 0 FE 0: tx_retime 0 FE 0: tx_interpolate 0 FE 0: tx_hilbert 0 FE 0: tx_keep_ve 0 FE 0: rx_pga_a 15 FE 0: rx_pga_b 15 FE 0: rx_dcs_ena 0 FE 0: rx_hs_duty_cycle 0 FE 0: rx_decimate 0 FE 0: rx_hilbert 0 FE 0: rx_keep_ve 0 FE 0: rx_inv_sync 0 FE 0: rx_twos_complement 0 FE 0: rx_retime 0 FE 0: mxfe_spi_raw 0x FE 0: rssi_config 0x TxDatapath-- FE 0: tx_sync_ena 1 FE 0: tx_data_sel 1 FE 0: tx_offset_i 120 FE 0: tx_offset_q 120 FE 0: tx_rate_i 3 FE 0: tx_rate_q 3 FE 0: tx_amplitude_i 0 FE 0: tx_amplitude_q 0 FE 0: tx_stepsize 1000 FE 0: tx_signal_mem_1 0x FE 0: tx_signal_mem_2 0x000100ff terminal count 255 step size 1 FE 0: tx_signal_mem_3 0x enable mask 0x1 FE 0: tx_ext_up_dn_ena 0 FE 0: tx_ext_up_dn 0 FE 0: tx_ext_data_i 0 FE 0: tx_ext_data_q 0 --RxDatapath-- FE 0: rx_test_sel 0 FE 0: rx_fft_sel 0 FE 0: rx_set_bias 0 FE 0: rx_resolution 0 --ChipScope-- local: scope 0 --HopControl-- local: hop_config_1 0x local: hop_config_2 0x
Data acquisition example spectra/14bit/256_10.txt // load signal from given file tx_on 1 // set parameter tx_on of front end 0 to 1
Bee2 and CR test bed demo DEMO
Next steps Use the./acquire utility to capture received signal and transfer it to BEE2 file system Use the extract_raw script to convert the binary dump file created by the “acquire” utility into a format readable my Matlab Run fft_rx matlab script on the resulting file.