An introduction to the group and its projects Tony McGregor

WAND Projects CRCNet Active Measurement IP Measurement protocol Passive Measurement Simulation Integrated measurement and simulation Emulation Network Physical layer switch IPv6 topology, mobile stacks, fast handover NZNOG ‘04

CRCNet Introduction Project started almost 2 years ago Rural communities were frustrated by low speed unreliable Internet access Develop a new platform suitable to deploy future generation (>>10Mbps) wireless networks in rural and remote areas based around a mesh architecture Funded by Foundation for Research Science and Technology

CRCNet Architecture

CRCNet Stage 1 – Build Trial Network Range of equipment 2.4Ghz (802.11b and g) Orinoco radio cards and APs Advantech and Soekris Biscuit PC Linksys wireless Ethernet bridges 5.8 GHz Proxim Quick bridge20 Trango

Current Topology

CRCNet Pirongia Site

CRCNet HSK Site

CRCNet MFR Site

CRCNet Web Casting Between Hamilton Zoo and the Fieldays site 6 wireless links

CRCNet Stage Two – Platform Design Routing protocols for mesh networks Link Layer Design Design of a new node

NLANR’s active measurement project Approx 140 monitors, mostly in the USA. International deployments a single AMP monitor in about a dozen other countries some national AMPs (Australia, Taiwan, Russia soon) Measure RTT loss topology throughput (on demand) NSF funded AMP Introduction

AMP USA Sites

AMP Architecture

AMP Demo

Design dedicated machines 1ms accuracy No GPS/CDMA 1 sample per minute Benefits easy and cheap => wide deployment full mesh manageable Limits no one-way delays (bidirectional traceroute, IPMP OWD) very short events missed AMP Cost vs Function

AMP Management

Beginnings of a New Zealand AMP mesh Waikato Auckland APE Ihug (offer) Can fund more monitors and maintenance need hosts (here?) hosts provide space, power and network AMP New Zealand

Current active measurement protocols have weaknesses multiple packets (overhead, phantom routes) measurement of components (reverse path, CPU) IPMP combines path and delay measurement in a single packet exchange with low router overhead IPMP Introduction

IPMP Architecture

IPMP Protocol (IPv4)

Router can use any timestamp it has available Resolving to real-time is not done in the packet forwarding critical path Uses a separate packet exchange (information request/reply) supplies real-time reference points other router information IPMP Timestamps

IPMP Information Reply

POM made better combined path and latency, no phantom routes etc lower overhead kernel based timestamps explicit clock information forward and reverse traceroute DoS resistant associates router interfaces One way delay from NTP Bandwidth Estimation Deployment (AMP, CRCnet) IPMP Uses

To support simulation work the group developed passive header capture hardware. Known as Dag cards Speeds from Ethernet to OC48 (2.5Gbps WAN) Spun off a startup Endace ( now OC192 better support Passive Measurement Overview

Capture IP headers or full packet Add accurate timestamp GPS or CDMA for external time Originally header trace focused real-time flow based security applications Optical splitter, electrical card relay or electrical tap Passive Measurement Dag Overview

Passive Measurement Dag 3 block diagram

Passive Dag 4.2

Passive WITS Traffic Archive Long traces from Auckland University and NZIX traces up to 45 days (3.2 billion packets) IP headers GPS timestamps Some analysis online Can fetch traces from NLANR Summary CD

ATM-TN based University of Calgary/Waikato partnership parallel BSDLite network stack (sort of) high bandwidth delay, mixed real-time/TCP NS-2 with FreeBSD stack new work network cradle b link layer Simulation Introduction

Simulation Example –TCP splitting

Simulation The simulation process

Bandwidth Mbps (E3) Delay 60ms TCP buffer size proxy bytes servers as measured MSS as measured US delay as measured NZ delay not simulated Simulation Example –TCP spliting, Network parameters

Simulation TCP Splitting – a single connection

Simulation Introduction

Simulation is only accessible to very large network operators and users AIM: Make simulation available to medium sized enterprises Integrate measurement and simulation FRST funded Messim Introduction

Topology discovery automated discovery of link layer devices Traffic Models further development of specific models (e.g. peer to peer) generic Extraction of simulation parameters from traces Extended range of network stack models Continuous validation Hardware flows analysis Messim Projects

Network stack FreeBSD 5 kernel Mozilla / Bash / KDE / etc. Kernel space User space Messim Network Stack Cradle

Network stack User space Cradle (~200 functions) Network Simulator

2d Empirical distribution Messim Generic models

Use WEKA machine learning algorithms to cluster classify For each cluster simplify the rule set into terms for a network manager produce an empirical distribution for each Allow simulations with different proportions of traffic Messim Generic models

There is a need for a structured environment in which to build networks in the laboratory validation of simulations testing on network equipment The emulation network is two racks of PCs that can be configured as routers end hosts delay Plus configuration and measurement support Emulation Network Introduction

Emulation Network Overview

Usage Is a public facility Has been used to debug AT switch Used network trace capture and replay then Ixia script Ihug traffic shaper Bandwidth estimator Development Physical layer switch Emulation Network Usage and development

64 Port FastEthernet Crossbar switch Fast / Flexible Reconfiguration Link Monitoring Latency Control Bandwidth limiting Self Documenting Network Topology Centralised Control Crossbar Switch Introduction

Crossbar Switch Block Diagram – Overview Mainboard 12.8Gb/s Uplink DaughterBoard 3.2Gb/s Mainboard Crossbar Latency Bandwidth Limiting Daughterboards Ethernet Interface Time Division MUX

Crossbar Switch Block Diagram –Mother board CPU FPGA 12.8Gb/s Uplink DaughterBoard DDR SDRAM (8GB max). SDRAM FLASH

Crossbar Switch Block Diagram – Daughter board PHY FPGA PHY 3.2Gb/s Ethernet Ports Uplink to Motherboard

Daughterboard Layout Crossbar Switch Daughter board Layout

Skitter for IPv6 Hope to capture the growth of the IPv6 internet Skamper Overview

Small devices One of the motivators for IPv6 is to provide addresses and other support for small devices a.k.a. cell phones implementing a stack for embedded devices little ram moderate CPU speeds prototype hardware development Fast handover between cells normally may exceed 2s reduce to around 150ms, l2 triggers, L3 preparation for handover and timing improvements in protocols IPv6 Stacks Overview

The New Zealand Network Operators Group has an annual conference The next one will be hosted by WAND Jan , at Waikato Discounted registration (free?) for students Hope to have a number of partial travel grants for students Could hold a parallel Academic Networking Conference need feedback NZNOG Conference