Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-23.

Slides:

Advertisements

Similar presentations

Conversion and Coding (12)10.

Advertisements

ECE2030 Introduction to Computer Engineering Lecture 13: Building Blocks for Combinational Logic (4) Shifters, Multipliers Prof. Hsien-Hsin Sean Lee School.

Using Carry-Save Adders For Radix- 4, Can Be Used to Generate 3a – No Booth’s Slight Delay Penalty from CSA – 3 Gates.

Multiplication Schemes Continued

Parallel Adder Recap To add two n-bit numbers together, n full-adders should be cascaded. Each full-adder represents a column in the long addition. The.

UNIVERSITY OF MASSACHUSETTS Dept

Chapter # 5: Arithmetic Circuits Contemporary Logic Design Randy H

Design of Arithmetic Circuits – Adders, Subtractors, BCD adders

Digital Arithmetic Wen-Hung Liao, Ph.D.. Objectives Perform binary addition, subtraction, multiplication, and division on two binary numbers. Add and.

CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.

Digital Circuits. Analog and Digital Signals Noise margins in Logic Circuits VMVM.

ECE 301 – Digital Electronics

M. Interleaving Montgomery High-Radix Comparison Improvement Adders CLA CSK Comparison Conclusion Improving Cryptographic Architectures by Adopting Efficient.

Chapter 5 Arithmetic Logic Functions. Page 2 This Chapter..  We will be looking at multi-valued arithmetic and logic functions  Bitwise AND, OR, EXOR,

Lecture 8 Floating point format

Binary Addition Addition Rules: = = = = = carry 1 1 carry 1 Example 1: Example 2:

Selecting a to Eliminate Carry Chain in SD For no carry, require.

General Fixed Radix Number Systems Nonredundant Positive radix, ß n digits in digit set Vector:

2-1 Chapter 2 - Data Representation Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Chapter Contents.

Data Representation and Computer Arithmetic

Digital Arithmetic and Arithmetic Circuits

COMPSCI 210 Semester Tutorial 1

Chapter 8 Problems Prof. Sin-Min Lee Department of Mathematics and Computer Science.

Chapter # 5: Arithmetic Circuits

CSE 241 Computer Organization Lecture # 9 Ch. 4 Computer Arithmetic Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.

Reconfigurable Computing - Multipliers: Options in Circuit Design John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on.

Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2.

UNIVERSITY OF ROSTOCK Institute of Applied Microelectronics and Computer Science Single-Rail Self-timed Logic Circuits in Synchronous Designs Frank Grassert,

Binary Adder DesignSpring Binary Adders. Binary Adder DesignSpring n-bit Addition –Ripple Carry Adder –Conditional Sum Adder –(Carry Lookahead.

Universal college of engineering & technology. .By Harsh Patel)

Computer Architecture Lecture 32 Fasih ur Rehman.

Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-9.

Unrolling Carry Recurrence

CEC 220 Digital Circuit Design Binary Codes

Unconventional Fixed-Radix Number Systems

CEC 220 Digital Circuit Design Binary Arithmetic & Negative Numbers Monday, January 13 CEC 220 Digital Circuit Design Slide 1 of 14.

Computer Architecture Lecture 16 Fasih ur Rehman.

Outline Binary Addition 2’s complement Binary Subtraction Half Adder

ECE 331 – Digital System Design Multi-bit Adder Circuits, Adder/Subtractor Circuit, and Multiplier Circuit (Lecture #12)

CEC 220 Digital Circuit Design Binary Arithmetic & Negative Numbers Fri, Aug 28 CEC 220 Digital Circuit Design Slide 1 of 14.

DIGITAL SYSTEMS Number systems & Arithmetic Rudolf Tracht and A.J. Han Vinck.

CEC 220 Digital Circuit Design

Full Tree Multipliers All k PPs Produced Simultaneously Input to k-input Multioperand Tree Multiples of a (Binary, High-Radix or Recoded) Formed at Top.

Computer Architecture Lecture 11 Arithmetic Ralph Grishman Oct NYU.

CEC 220 Digital Circuit Design Binary Codes Mon, Aug 31 CEC 220 Digital Circuit Design Slide 1 of 14.

ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill.

1 Lecture 14 Binary Adders and Subtractors. 2 Overview °Addition and subtraction of binary data is fundamental Need to determine hardware implementation.

Lecture #23: Arithmetic Circuits-1 Arithmetic Circuits (Part I) Randy H. Katz University of California, Berkeley Fall 2005.

ECE DIGITAL LOGIC LECTURE 15: COMBINATIONAL CIRCUITS Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 10/20/2015.

MicroProcessors Lec. 4 Dr. Tamer Samy Gaafar. Course Web Page —

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle.

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle.

Reconfigurable Computing - Options in Circuit Design John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound,

Reconfigurable Computing - Options in Circuit Design John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound,

Fuw-Yi Yang1 數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi.

High Computation Mahendra Sharma. Hybrid number representation The hybrid number representations proposed are capable of bounding the maximum length of.

Lecture 4: Digital Systems & Binary Numbers (4)

Addition and Subtraction

CHAPTER 4: Representing Integer Data

Reference: Moris Mano 4th Edition Chapter 4

Exercise: Add these two single precision IEEE 754 numbers: … …0 Left number: 1.101x24 Right number: 1.011x 22= x24.

CSE 575 Computer Arithmetic Spring 2005 Mary Jane Irwin (www. cse. psu

Unconventional Fixed-Radix Number Systems

Arithmetic Circuits (Part I) Randy H

UNIVERSITY OF MASSACHUSETTS Dept

Number Systems and Circuits for Addition

Digital Systems and Binary Numbers

Chapter 5 -Part 3.

Han Liu Partner: Dongdong Chen Supervisor: Seok-Bum Ko

Counter Fundamentals Presented by :

Presentation transcript:

Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-23

Outline Information of literature Background Carry Free Adder Limited Carry Free Adder Synthesis Result Conclusion 2

Information of literature Reliable Binary Signed Digit Number Adder Design F. Kharbash, G. M. Chaudhry IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07) 3

Background Fast Adder Architecture Carry Skip Adder Carry Look-ahead Adder Carry Save Adder Carry Free Adder Limited Carry Free Adder 4

Carry Free Addition 1/4 Redundancy Representation of numbers is not unique Redundancy may result from narrowing the range of represented values (e.g. 1's compl.) Redundancy may result from adopting the digit set wider than radix ({-1,0,1} in radix 2) Conversion is a carry-propagate (slow) process

Carry Free Addition 2/4 Reduction of digit set by carry propagation by only one position P=10*T+W P is preliminary results T is transfer digits W is immediate sums

Carry Free Addition 3/4 Two-Stage Carry Free Adder

Carry Free Addition 4/4 Coding Schemes influence on complexity sign+value BSD: -1 (11), 0 (00), 1 (01) 2's complement BSD: -1 (11), 0 (00), 1 (01) negative-positive flags ([-1,1] only) BSD: -1 (10), 0 (00), 1 (01) 1-out-of-n BSD: -1 (100), 0 (010), 1 (001)

Limited Carry Free Addition 1/3 When redundancy is not enough, the free carry propagation cannot be guaranteed ? ? H H ? ? X Y p e w t S

Limited Carry Free Addition 2/3 Three -Stage Limited Carry Free Adder

Limited Carry Free Addition 3/3 1-out-of-3 SD number

Synthesis Result 1/2 Timing Delay Statistic under 0.18 um technology unit is nS

Synthesis Result 2/2 Area and Power Consumption Statistic

Conclusion Propagation delay in Carry Free Adder is independent with input bit width Different coding schemes have different complexity and timing delay Conversion after the CFA still generate delay CFA is suitable in multiple addition stages process CFA is suitable if redundancy is enough (ie. BCD number in decimal addition)

Question Thanks! 15